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A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations

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Ning GeAuthors Info & Claims

DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe

Pages 1285 - 1290

Published: 14 March 2016 Publication History

Abstract

Multi-level cell spin-transfer torque random access memory (MLC STT-RAM) demonstrates great potentials in on-chip cache design for its high storage density and non-volatility but also suffers from the degraded access time, reliability and energy efficiency. The existing MLC STT-RAM cache designs primarily focus on the performance and energy optimizations, however, often ignore the crucial demand for reliability. In this work, we propose a tri-region MLC STT-RAM cache design (TMSC) to simultaneously meet the requirements of performance, energy, and reliability. The tri-region MLC STT-RAM cache is optimized partitioned into fast, mixed, and slow ways according to different access performance, energy and reliability. A new error correction code (ECC) scheme, namely, non-uniform strength ECC (NUS-ECC), is also developed to tolerate the different bit failure rates in these ways. Compared to the latest performance-driven MLC STT-RAM cache design with pessimistic ECC scheme, our TMSC technique can improve the system performance and energy by averagely 9.3% and 9.4%, respectively, for various applications. The additional area cost associated with NUS-ECC is limited by 3.2% compared to the pessimistic ECC scheme.

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Cited By

Li BPei YWen W(2018)Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAMACM Journal on Emerging Technologies in Computing Systems10.1145/315483614:1(1-20)Online publication date: 8-Mar-2018
https://dl.acm.org/doi/10.1145/3154836
Liu ZMao MLiu TWang XWen WChen YLi HWang DPei YGe N(2018)TriZoneIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.278386037:10(1985-1998)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2783860
Chen XKhoshavi NDeMara RWang JHuang DWen WChen Y(2017)Energy-Aware Adaptive Restore Schemes for MLC STT-RAM CacheIEEE Transactions on Computers10.1109/TC.2016.262524566:5(786-798)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TC.2016.2625245

A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information & Contributors

Information

Published In

cover image Guide Proceedings

DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe

March 2016

1779 pages

ISBN:9783981537062

General Chair:
Luca Fanucci
University of Pisa, IT
,
Program Chair:
Jürgen Teich
Friedrich-Alexander-Universität, Erlangen-Nürnberg, DE

Sponsors

IMEC: IMEC
Systematic: Systematic Paris-Region Systems & ICT Cluster
DREWAG: DREWAG
AENEAS: AENEAS
Technical University of Dresden
CMP: Circuits Multi Projets
PENTA: PENTA
CISCO
OFFIS: Oldenburger Institut für Informatik
Goethe University: Goethe University Frankfurt

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 14 March 2016

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Cited By

Li BPei YWen W(2018)Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAMACM Journal on Emerging Technologies in Computing Systems10.1145/315483614:1(1-20)Online publication date: 8-Mar-2018
https://dl.acm.org/doi/10.1145/3154836
Liu ZMao MLiu TWang XWen WChen YLi HWang DPei YGe N(2018)TriZoneIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.278386037:10(1985-1998)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2783860
Chen XKhoshavi NDeMara RWang JHuang DWen WChen Y(2017)Energy-Aware Adaptive Restore Schemes for MLC STT-RAM CacheIEEE Transactions on Computers10.1109/TC.2016.262524566:5(786-798)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TC.2016.2625245

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