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Energy reduction for STT-RAM using early write termination

Authors:

Youtao ZhangAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 264 - 268

https://doi.org/10.1145/1687399.1687448

Published: 02 November 2009 Publication History

Abstract

The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too high.

In this paper, we propose Early Write Termination (EWT), a novel technique to significantly reduce write energy with no performance penalty. EWT can be implemented with low complexity and low energy overhead. Our evaluation shows that up to 80% of write energy reduction can be achieved through EWT, resulting 33% less total energy consumption, and 34% reduction in ED². These results indicate that EWT is an effective and practical scheme to improve the energy efficiency of a STT-RAM cache.

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Cited By

ASANO KNATSUI MHANYU T(2024)Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network HardwareIEICE Transactions on Information and Systems10.1587/transinf.2023LOP0007E107.D:8(958-965)Online publication date: 1-Aug-2024
https://doi.org/10.1587/transinf.2023LOP0007
Kumari SYadav R(2024)Survey On the Sensing Techniques Used for Spin Transfer Torque MRAMJournal of The Institution of Engineers (India): Series B10.1007/s40031-024-01111-1105:5(1469-1496)Online publication date: 18-Jul-2024
https://doi.org/10.1007/s40031-024-01111-1
Rajpoot JVerma S(2023)Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory ApplicationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.324298970:7(2630-2634)Online publication date: Jul-2023
https://doi.org/10.1109/TCSII.2023.3242989
Show More Cited By

Index Terms

Energy reduction for STT-RAM using early write termination
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Conferences

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CAS
IEEE Council on Electronic Design Automation (CEDA)

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 November 2009

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ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

ASANO KNATSUI MHANYU T(2024)Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network HardwareIEICE Transactions on Information and Systems10.1587/transinf.2023LOP0007E107.D:8(958-965)Online publication date: 1-Aug-2024
https://doi.org/10.1587/transinf.2023LOP0007
Kumari SYadav R(2024)Survey On the Sensing Techniques Used for Spin Transfer Torque MRAMJournal of The Institution of Engineers (India): Series B10.1007/s40031-024-01111-1105:5(1469-1496)Online publication date: 18-Jul-2024
https://doi.org/10.1007/s40031-024-01111-1
Rajpoot JVerma S(2023)Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory ApplicationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.324298970:7(2630-2634)Online publication date: Jul-2023
https://doi.org/10.1109/TCSII.2023.3242989
Rajpoot JGupta MVerma S(2023)Enhancing the Reliability of Hybrid MTJ/CMOS Circuits with Auto Write Termination2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)10.1109/IPFA58228.2023.10249113(1-6)Online publication date: 24-Jul-2023
https://doi.org/10.1109/IPFA58228.2023.10249113
Zhang GJiang Y(2023)Novel multi-bit parallel pipeline-circuit design for STT-MRAMAIP Advances10.1063/9.000057613:2(025010)Online publication date: 1-Feb-2023
https://doi.org/10.1063/9.0000576
Jeong JZeng JJung CWeissman JChandra AGavrilovska ATiwari D(2022)CapriProceedings of the 31st International Symposium on High-Performance Parallel and Distributed Computing10.1145/3502181.3531474(71-83)Online publication date: 27-Jun-2022
https://dl.acm.org/doi/10.1145/3502181.3531474
Asifuzzaman KVerdejo RRadojković P(2022)Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level SimulationACM Transactions on Embedded Computing Systems10.1145/347683821:1(1-25)Online publication date: 14-Jan-2022
https://dl.acm.org/doi/10.1145/3476838
Zhang GJiang Y(2022)Fast Writing Strategy of STT-MRAM With Pipeline ArchitectureIEEE Transactions on Magnetics10.1109/TMAG.2021.313660458:8(1-5)Online publication date: Aug-2022
https://doi.org/10.1109/TMAG.2021.3136604
Singh RVerma SMittal S(2022)FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance EnhancementIEEE Transactions on Electron Devices10.1109/TED.2022.321720669:12(6699-6704)Online publication date: Dec-2022
https://doi.org/10.1109/TED.2022.3217206
Kim YJeon YChoi HGuyot CCassuto Y(2022)Optimizing Write Fidelity of MRAMs by Alternating Water-Filling AlgorithmIEEE Transactions on Communications10.1109/TCOMM.2022.319086870:9(5825-5836)Online publication date: Sep-2022
https://doi.org/10.1109/TCOMM.2022.3190868
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