More Web Proxy on the site http://driver.im/

research-article

A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric

Authors:

Kostas Siozios,

Vasilis F. Pavlidis,

Dimitrios SoudrisAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 5, Issue 1

Article No.: 4, Pages 1 - 23

https://doi.org/10.1145/2133352.2133356

Published: 23 March 2012 Publication History

Abstract

A heterogeneous interconnect architecture can be a useful approach for the design of 3-D FPGAs. A methodology to investigate heterogeneous interconnection schemes for 3-D FPGAs under different 3-D fabrication technologies is proposed. Application of the proposed methodology on benchmark circuits demonstrates an improvement in delay, power consumption, and total wire-length of approximately 41%, 32%, and 36%, respectively, as compared to 2-D FPGAs. These improvements are additional to reducing the number of interlayer connections. The fewer interlayer connections are traded off for a higher yield. An area model to evaluate this trade-off is presented. Results indicate that a heterogeneous 3-D FPGA requires 37% less area as compared to a homogeneous 3-D FPGA. Consequently, the heterogeneous FPGAs can exhibit a higher manufacturing yield. A design toolset is also developed to support the design and exploration of various performance metrics for the proposed 3-D FPGAs.

References

[1]

Ababei, C., Feng, Y., Goplen, B., Mogal, H., Zhang, T., Bazargan, K., and Sapatnekar, S. 2005. Placement and routing in 3-d integrated circuits. IEEE Des. Test 22, 6, 520--531.

Digital Library

[2]

Alpert, C. and Kahng, A. 1995. Recent directions in netlist partitioning: A survey. Integration VLSI J. 19, 1, 1--81.

Digital Library

[3]

Betz, V. and Rose, J. 1996. Directional bias and non-uniformity in fpga global routing architectures. In Proceedings of the Digest of Technical Papers. IEEE/ACM International Conference on Computer-Aided Design. 652--659.

Digital Library

[4]

Betz, V., Rose, J., and Marquardt, A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers.

Digital Library

[5]

Beyne, E. 2004. 3-d interconnection and packaging: Impending reality or still a dream&quest; In Proceedings of the International IEEE Solid-State Circuits Conference. Vol. 1. 138--139.

[6]

Britton, B., Oh, Y., Oswald, W., Nguyen, H., Singh, S., Lee, G., Wai-Bor, L., Spivak, C., Steward, J., and Chen, C. 1994. Second generation orca architecture utilizing 0.5m process enhances the speed and usable gate capacity of fpgas. In Proceedings of the IEEE International Conference on ASIC. 474--478.

[7]

Das, S., Fan, A., Chen, K. N., Tan, C., Checka, N., and Reif, R. 2004. Technology, performance, and computer aided design of three dimensional integrated circuits. In Proceedings of the International IEEE Symposium on Physical Design. 108--115.

Digital Library

[8]

Dong, C., Chen, D., Haruehanroengra, S., and Wang, W. 2007. 3-d nfpga: A reconfigurable architecture for 3-d cmos/nanomaterial hybrid digital circuits. IEEE Trans. Circ. Syst. 54, 11, 2489--2501.

[9]

Enbody, R. J., Lynn, G., and Tan, K. H. 1991. Routing the 3-d chip. In Proceedings of the IEEE/ACM Design Automation Conference (DAC). 132--137.

Digital Library

[10]

Fang, D., Peng, S., Lafrieda, C., and Manohar, R. 2006. A three-tier asynchronous fpga. In Proceedings of the International VLSI/ULSI Multilevel Interconnection Conference.

[11]

Gayasen, A., Vijaykrishnan, N., Kandemir, M., and Rahman, A. 2008. Designing a 3-d fpga: Switch box architecture and thermal issues. IEEE Trans. VLSI Syst. 16, 7, 882--893.

Digital Library

[12]

Gupta, S., Hilbert, M., Hong, S., and Patti, R. 2004. Techniques for producing 3d ics with high-density interconnect. In Proceedings of the VLSI Multi-Level Interconnection Conference.

[13]

Lamoureux, J. Benchmark circuits. http://www.ece.ubc.ca/~julienl/scripts/stitch_blifs.pl.

[14]

Le, R., Reda, S., and Bahar, R. 2009. High-performance, cost-effective heterogeneous 3d fpga architectures. In Proceedings of the ACM Great Lakes Symposium on VLSI (GLS-VLSI). 251--256.

Digital Library

[15]

Leijten-Nowak, K. and Meerbergen, J. 2003. An fpga architecture with enhanced datapath functionality. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA). 195--204.

Digital Library

[16]

Lin, M., El Gamal, A., Lu, Y., and Wong, S. 2007. Performance benefits of monolithically stacked 3-d fpga. IEEE Trans. Comput. Aid. Desi. Integra. Circu. Syst. 26, 2, 216--229.

Digital Library

[17]

McMurchie, L. and Ebeling, C. 1995. Pathfinder: a negotiation-based performance-driven router for fpgas. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. 111--117.

Digital Library

[18]

MCNC. Standard cell benchmark circuits from the Microelectronics Center of North Carolina. http://vlsicad.cs.binghamton.edu/gz/pdworkshop91.tgz.

[19]

Meleis, W., Leeser, M., Zavracky, P., and Vai, M. 1997. Architectural design of a three dimensional fpga. In Proceedings of the 17th Conference on Advanced Research in VLSI. 256--269.

Digital Library

[20]

Pavlidis, V. F. and Friedman, E. G. 2009. Three-Dimensional Integrated Circuit Design. Morgan Kaufmann Publishers.

Digital Library

[21]

Rahman, A. 2001. System-level performance evaluation of three-dimensional integrated circuits. Ph.D. thesis, Department of Electrical and Computer Science, Massachusetts Insitute of Technology.

[22]

Roy, J., Adya, S., Papa, D., and Markov, I. 2006. Min-cut floorplacement. IEEE Trans. Comput. Aid. Desi. Integr. Circ. Syst. 25, 7, 1313--1326.

Digital Library

[23]

Savidis, I. and Friedman, E. 2008. Electrical modeling and characterization of 3-d vias. In Proceedings of the International IEEE Symposium on Circuits and Systems (ISCAS). 784--787.

[24]

Savidis, I. and Friedman, E. 2009. Closed-form expressions of 3-d via resistance, inductance, and capacitance. IEEE Trans. Electron Dev. 56, 9, 1873--1881.

[25]

Selvakkumaran, N. and Karypis, G. 2006. Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization. IEEE Trans. Comput. Aid. Desi. Integr. Circ. Syst. 25, 3, 504--517.

Digital Library

[26]

Siozios, K., Bartzas, A., and Soudris, D. 2008. Architecture-level exploration of alternative interconnection schemes targeting 3d fpgas: A software-supported methodology. Int. J. Reconfig. Comput.

[27]

Siozios, K., Papanikolaou, A., and Soudris, D. 2008b. A method and tool for early design/technology search-space exploration for 3d ics. In Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). 359--364.

[28]

Siozios, K., Pavlidis, V. F., and Soudris, D. 2009. A software-supported methodology for exploring interconnection architectures targeting 3-d fpgas. In Proceedings of the Design, Automation and Testing in Europe (DATE). 172--177.

Digital Library

[29]

Siozios, K. and Soudris, D. 2008. A power-aware placement and routing algorithm targeting 3d fpgas. J. Low-Power Electron. 4, 3, 275--289.

[30]

Topol, A., Tulipe, D., Shi, L., Frank, D., Bernstein, K., Steen, S., Kuman, A., Singco, G., Young, A., Guarini, K., and Ieong, M. 2006. Three-dimensional integrated circuits. IBM J. Resour. Devel. 50, 4/5, 491--506.

Digital Library

[31]

Tredennick, N. and Shimamoto, B. 2003. The rise of reconfigurable systems. In Engineering of Reconfigurable Systems and Algorithms. 3--12.

[32]

Velenis, D., Stucchi, M., Marinissen, E. J., and Beyne, E. 2009. Impact of design choices on 3d sic manufacturing cost. In Proceedings of the Workshop on 3-D Integration, at Design, Automation, and Testing in Europe Conference (DATE).

[33]

Wang, G., Sivaswamy, S., Ababei, C., Bazargan, K., Kastner, R., and Bozorgzadeh, E. 2006. Statistical analysis and design of harp routing pattern fpgas. IEEE Trans. Comput. Aid. Desi. Integr. Circ. Syst. 25, 10, 2088--2102.

Digital Library

[34]

Weerasekera, R., Pamunuwa, D., Zheng, L. R., and Tenhunnen, H. 2009. Two-dimensional and three-dimensional integration of heterogeneous electronic systems under cost, performance, and technological constraints. IEEE Trans. Comput. Aid. Des. Integr. Circu. Syst. 28, 8, 1237--1250.

Digital Library

[35]

XILINX. http://www.xilinx.com.

[36]

Yu, C. 2006. The 3rd dimension—more life for Moore's law. In Proceedings of the International Microsystems, Packaging, Assembly Conference. 1--6.

Cited By

Zhao QAmagasaki MIida MYoshida T(2020)Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network2020 Eighth International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR51075.2020.00040(235-241)Online publication date: Nov-2020
https://doi.org/10.1109/CANDAR51075.2020.00040
AMAGASAKI MIKEBE MZHAO QIIDA MSUEYOSHI T(2018)Three Dimensional FPGA Architecture with Fewer TSVsIEICE Transactions on Information and Systems10.1587/transinf.2017RCP0008E101.D:2(278-287)Online publication date: 2018
https://doi.org/10.1587/transinf.2017RCP0008
Singh A(2017)Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA ArchitectureField - Programmable Gate Array10.5772/67257Online publication date: 31-May-2017
https://doi.org/10.5772/67257
Show More Cited By

Index Terms

A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
1. Computer systems organization
  1. Architectures

Recommendations

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencies and logic densities is also important for the Field-Programmable Gate ...
Packing Techniques for Virtex-5 FPGAs

Packing is a key step in the FPGA tool flow that straddles the boundaries between synthesis, technology mapping and placement. Packing strongly influences circuit speed, density, and power, and in this article, we consider packing in the commercial FPGA ...
Architecture-specific packing for virtex-5 FPGAs
FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA -- the Xilinx Virtex-5 FPGA. Two aspects of packing are discussed: 1)packing for general logic ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 5, Issue 1

March 2012

148 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2133352

Issue’s Table of Contents

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 March 2012

Revised: 01 October 2011

Accepted: 01 August 2011

Received: 01 July 2010

Published in TRETS Volume 5, Issue 1

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

17
Total Citations
View Citations
298
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)1

Reflects downloads up to 19 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Zhao QAmagasaki MIida MYoshida T(2020)Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network2020 Eighth International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR51075.2020.00040(235-241)Online publication date: Nov-2020
https://doi.org/10.1109/CANDAR51075.2020.00040
AMAGASAKI MIKEBE MZHAO QIIDA MSUEYOSHI T(2018)Three Dimensional FPGA Architecture with Fewer TSVsIEICE Transactions on Information and Systems10.1587/transinf.2017RCP0008E101.D:2(278-287)Online publication date: 2018
https://doi.org/10.1587/transinf.2017RCP0008
Singh A(2017)Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA ArchitectureField - Programmable Gate Array10.5772/67257Online publication date: 31-May-2017
https://doi.org/10.5772/67257
Siozios KSoudris D(2016)A Customizable Framework for Application Implementation onto 3-D FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252942135:11(1783-1796)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TCAD.2016.2529421
Chtourou SMarrakchi ZAmouri EPangracious VMehrez HAbid M(2016)Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)10.1109/PDP.2016.77(635-642)Online publication date: Feb-2016
https://doi.org/10.1109/PDP.2016.77
Danassis PSiozios KSoudris D(2016)Parallel application placement onto 3-D reconfigurable architectures2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST.2016.7495108(1-4)Online publication date: May-2016
https://doi.org/10.1109/MOCAST.2016.7495108
Pangracious VMarrakchi ZMehrez H(2015)Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGAIEEE Micro10.1109/MM.2014.5735:6(48-59)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1109/MM.2014.57
Pangracious VMarrakchi ZMehrez HPangracious VMarrakchi ZMehrez H(2015)Physical Design and Implementation of 3D Tree-Based FPGAsThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_8(169-199)Online publication date: 26-Jun-2015
https://doi.org/10.1007/978-3-319-19174-4_8
Pangracious VMarrakchi ZMehrez HPangracious VMarrakchi ZMehrez H(2015)Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and TechnologiesThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_6(117-146)Online publication date: 26-Jun-2015
https://doi.org/10.1007/978-3-319-19174-4_6
Pangracious VMarrakchi ZMehrez HPangracious VMarrakchi ZMehrez H(2015)Three-Dimensional FPGAs: Configuration and CAD DevelopmentThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_5(95-116)Online publication date: 26-Jun-2015
https://doi.org/10.1007/978-3-319-19174-4_5
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents