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Article

An FPGA architecture with enhanced datapath functionality

Authors:

Katarzyna Leijten-Nowak,

Jef L. van MeerbergenAuthors Info & Claims

FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

Pages 195 - 204

https://doi.org/10.1145/611817.611846

Published: 23 February 2003 Publication History

Abstract

Although FPGAs are a cost-efficient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efficiency gap makes FPGAs less suitable for high-volume cost-sensitive applications (e.g. embedded systems).We show that the intrinsic cost of traditional general-purpose FPGAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity' being a trade-off between fine and coarse granularity required for the implementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs, and, assuming a standard-cell implementation, a 1.6-2.8 lower datapath mapping cost. A modified mixed-grain architecture with the ALU-like functionality reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efficiency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if characteristics of a target application domain are known a priority.

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Cited By

Siozios KSoudris D(2016)A Customizable Framework for Application Implementation onto 3-D FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252942135:11(1783-1796)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TCAD.2016.2529421
Siozios KSavidis ISoudris D(2016)A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818369(336-341)Online publication date: Jul-2016
https://doi.org/10.1109/SAMOS.2016.7818369
Bostelmann TSawitzki S(2015)Towards a guided design flow for heterogeneous reconfigurable architectures2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293991(1-2)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293991
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Index Terms

An FPGA architecture with enhanced datapath functionality
1. Hardware

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Published In

cover image ACM Conferences

FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

February 2003

256 pages

ISBN:158113651X

DOI:10.1145/611817

General Chair:
Steve Trimberger
Xilinx
,
Program Chair:
Russ Tessier
University of Massachusetts - Amherst

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 23 February 2003

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FPGA03

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FPGA03: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2003

February 23 - 25, 2003

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Siozios KSoudris D(2016)A Customizable Framework for Application Implementation onto 3-D FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252942135:11(1783-1796)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TCAD.2016.2529421
Siozios KSavidis ISoudris D(2016)A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818369(336-341)Online publication date: Jul-2016
https://doi.org/10.1109/SAMOS.2016.7818369
Bostelmann TSawitzki S(2015)Towards a guided design flow for heterogeneous reconfigurable architectures2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293991(1-2)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293991
Bostelmann TSawitzki S(2015)A Heterogeneous Architecture Template for Application Domain Specific Reconfigurable LogicProceedings of the 2015 Austrian Workshop on Microelectronics10.1109/Austrochip.2015.12(9-14)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1109/Austrochip.2015.12
Siozios KPavlidis VSoudris D(2012)A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabricACM Transactions on Reconfigurable Technology and Systems10.1145/2133352.21333565:1(1-23)Online publication date: 23-Mar-2012
https://dl.acm.org/doi/10.1145/2133352.2133356
Parandeh-Afshar HZgheib GBrisk PIenne PWawrzynek JCompton K(2011)Reducing the pressure on routing resources of FPGAs with generic logic chainsProceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950458(237-246)Online publication date: 27-Feb-2011
https://dl.acm.org/doi/10.1145/1950413.1950458
Siozios KPavlidis VSoudris DBenini LDe Micheli GAl-Hashimi BMueller W(2009)A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874662(172-177)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874662
Parandeh-Afshar HBrisk PIenne P(2009)An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 CompressorACM Transactions on Reconfigurable Technology and Systems10.1145/1575774.15757782:3(1-42)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1145/1575774.1575778
Cevrero AAthanasopoulos PParandeh-Afshar HVerma ANiaki HNicopoulos CGurkaynak FBrisk PLeblebici YIenne P(2009)Field Programmable Compressor TreesACM Transactions on Reconfigurable Technology and Systems10.1145/1534916.15349232:2(1-36)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1145/1534916.1534923
Ho CYu CLeong PLuk WWilton S(2009)Floating-point FPGAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200661617:12(1709-1718)Online publication date: 1-Dec-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2006616
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