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View all- Olivares JPalomares J(2012)Dual-core motion estimation processor22nd International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2012.6339217(603-606)Online publication date: Aug-2012
Reconfigurable architecture for VBSME with variable pixel precision
Article No.: 3, Pages 1 - 11
Abstract
Current video coding standards, e.g. MPEG-4 H.264/AVC, include Variable Block Size Motion Estimation, in this paper, this process is implemented by a reconfigurable architecture based on Signed Digit arithmetic. Bit serial computation is applied to reconfigure pixel precision. The reconfigurable architectural model is extremely simple to reconfigure. Pixel truncation is used to speed up computation saving up 23.5% of clock cycles for 4-bit precision. This design allows to process all motion vectors of a block in just one iteration. This system has been implemented in FPGA, and HDTVp results are presented. Main characteristics, of this architecture are: very reduced cost, high performance, and reconfigurable pixel precision, these features could be useful in mobile devices.
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Index Terms
- Reconfigurable architecture for VBSME with variable pixel precision
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Publication History
Published: 23 March 2012
Accepted: 01 July 2011
Revised: 01 May 2011
Received: 01 March 2011
Published in TRETS Volume 5, Issue 1
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View all- Olivares JPalomares J(2012)Dual-core motion estimation processor22nd International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2012.6339217(603-606)Online publication date: Aug-2012
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