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DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip

Published: 04 June 2011 Publication History

Abstract

With the emergence of many-core architectures, it is quite likely that multiple applications will run concurrently on a system. Existing locally and globally adaptive routing algorithms largely overlook issues associated with workload consolidation. The shortsightedness of locally adaptive routing algorithms limits performance due to poor network congestion avoidance. Globally adaptive routing algorithms attack this issue by introducing a congestion propagation network to obtain network status information beyond neighboring nodes. However, they may suffer from intra- and inter-application interference during output port selection for consolidated workloads, coupling the behavior of otherwise independent applications and negatively affecting performance.
To address these two issues, we propose Destination-Based Adaptive Routing (DBAR). We design a novel low-cost congestion propagation network that leverages both local and non-local network information for more accurate congestion estimates. Thus, DBAR offers effective adaptivity for congestion beyond neighboring nodes. More importantly, by integrating the destination into the selection function, DBAR mitigates intra- and inter-application interference and offers dynamic isolation among regions. Experimental results show that DBAR can offer better performance than the best baseline algorithm for all measured configurations; it is well suited for workload consolidation. The wiring overhead of DBAR is low and DBAR provides improvement in the energy-delay product for medium and high injection rates.

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Cited By

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  • (2024)LBDR: A load-balanced deadlock-free routing strategy for chiplet systemsIntegration10.1016/j.vlsi.2024.10214996(102149)Online publication date: May-2024
  • (2023)Power: Multi-Capatibility Adaptive Routing for Network-an-Chips2023 3rd International Conference on Neural Networks, Information and Communication Engineering (NNICE)10.1109/NNICE58320.2023.10105691(751-754)Online publication date: 24-Feb-2023
  • (2023)A Survey of Machine Learning for Network-on-ChipsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104778(104778)Online publication date: Nov-2023
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      Published In

      cover image ACM SIGARCH Computer Architecture News
      ACM SIGARCH Computer Architecture News  Volume 39, Issue 3
      ISCA '11
      June 2011
      462 pages
      ISSN:0163-5964
      DOI:10.1145/2024723
      Issue’s Table of Contents
      • cover image ACM Conferences
        ISCA '11: Proceedings of the 38th annual international symposium on Computer architecture
        June 2011
        488 pages
        ISBN:9781450304726
        DOI:10.1145/2000064
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 04 June 2011
      Published in SIGARCH Volume 39, Issue 3

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      Author Tags

      1. networks-on-chip
      2. routing algorithm
      3. workload consolidation

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      Cited By

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      • (2024)LBDR: A load-balanced deadlock-free routing strategy for chiplet systemsIntegration10.1016/j.vlsi.2024.10214996(102149)Online publication date: May-2024
      • (2023)Power: Multi-Capatibility Adaptive Routing for Network-an-Chips2023 3rd International Conference on Neural Networks, Information and Communication Engineering (NNICE)10.1109/NNICE58320.2023.10105691(751-754)Online publication date: 24-Feb-2023
      • (2023)A Survey of Machine Learning for Network-on-ChipsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104778(104778)Online publication date: Nov-2023
      • (2022)Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research DirectionNetwork-on-Chip - Architecture, Optimization, and Design Explorations10.5772/intechopen.97262Online publication date: 6-Apr-2022
      • (2022)A Hybrid Selection Strategy Based on Traffic Analysis for Improving Performance in Networks on ChipJournal of Sensors10.1155/2022/31121702022(1-19)Online publication date: 26-Apr-2022
      • (2022)Congestion management in high-performance interconnection networks using adaptive routing notificationsThe Journal of Supercomputing10.1007/s11227-022-04926-179:7(7804-7834)Online publication date: 7-Dec-2022
      • (2021)A survey on emerging issues in interconnection networksInternational Journal of Internet Technology and Secured Transactions10.1504/ijitst.2021.11351211:2(131-159)Online publication date: 1-Jan-2021
      • (2021)Remote Control: A Simple Deadlock Avoidance Scheme for Modular Systems-on-ChipIEEE Transactions on Computers10.1109/TC.2020.302968270:11(1928-1941)Online publication date: 1-Nov-2021
      • (2020)Reliable Weighted Globally Congestion Aware Routing for Network on ChipInternational Journal of Embedded and Real-Time Communication Systems10.4018/IJERTCS.202007010311:3(48-66)Online publication date: 1-Jul-2020
      • (2019)A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparisonInternational Journal of Computers and Applications10.1080/1206212X.2019.167952945:1(27-35)Online publication date: 20-Oct-2019
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