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Evaluating Bufferless Flow Control for On-chip Networks

Authors:

George Michelogiannakis,

Daniel Sanchez,

William J. Dally,

Christos KozyrakisAuthors Info & Claims

NOCS '10: Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

Pages 9 - 16

https://doi.org/10.1109/NOCS.2010.10

Published: 03 May 2010 Publication History

Abstract

With the emergence of on-chip networks, the power consumed by router buffers has become a primary concern. Bufferless flow control addresses this issue by removing router buffers, and handles contention by dropping or deflecting flits. This work compares virtual-channel (buffered) and deflection (packet-switched bufferless) flow control. Our evaluation includes optimizations for both schemes: buffered networks use custom SRAM-based buffers and empty buffer bypassing for energy efficiency, while bufferless networks feature a novel routing scheme that reduces average latency by 5%. Results show that unless process constraints lead to excessively costly buffers, the performance, cost and increased complexity of deflection flow control outweigh its potential gains: bufferless designs are only marginally (up to 1.5%) more energy efficient at very light loads, and buffered networks provide lower latency and higher throughput per unit power under most conditions.

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Cited By

Soares Indrusiak LBurns A(2023)Real-Time Guarantees in Routerless Networks-on-ChipACM Transactions on Embedded Computing Systems10.1145/361653922:5(1-27)Online publication date: 26-Sep-2023
https://dl.acm.org/doi/10.1145/3616539
Zhou WOuyang YLu YLiang H(2022)A router architecture with dual input and dual output channels for Networks-on-ChipMicroprocessors & Microsystems10.1016/j.micpro.2022.10446490:COnline publication date: 1-Apr-2022
https://dl.acm.org/doi/10.1016/j.micpro.2022.104464
Parane KM PTalawar B(2020)LBNoCACM Transactions on Design Automation of Electronic Systems10.1145/336599425:1(1-26)Online publication date: 15-Jan-2020
https://dl.acm.org/doi/10.1145/3365994
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Published In

cover image Guide Proceedings

NOCS '10: Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

May 2010

255 pages

ISBN:9780769540535

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 May 2010

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Cited By

Soares Indrusiak LBurns A(2023)Real-Time Guarantees in Routerless Networks-on-ChipACM Transactions on Embedded Computing Systems10.1145/361653922:5(1-27)Online publication date: 26-Sep-2023
https://dl.acm.org/doi/10.1145/3616539
Zhou WOuyang YLu YLiang H(2022)A router architecture with dual input and dual output channels for Networks-on-ChipMicroprocessors & Microsystems10.1016/j.micpro.2022.10446490:COnline publication date: 1-Apr-2022
https://dl.acm.org/doi/10.1016/j.micpro.2022.104464
Parane KM PTalawar B(2020)LBNoCACM Transactions on Design Automation of Electronic Systems10.1145/336599425:1(1-26)Online publication date: 15-Jan-2020
https://dl.acm.org/doi/10.1145/3365994
Kapre NKrishna T(2018)FastTrackProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00067(739-751)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00067
Mische JMellwig CStegmeier AFrieb MUngerer T(2017)Minimally buffered deflection routing with in-order delivery in a torusProceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip10.1145/3130218.3130227(1-8)Online publication date: 19-Oct-2017
https://dl.acm.org/doi/10.1145/3130218.3130227
Kapre NGray J(2017)HopliteACM Transactions on Reconfigurable Technology and Systems10.1145/302748610:2(1-24)Online publication date: 22-Mar-2017
https://dl.acm.org/doi/10.1145/3027486
Zhao XMa SLiu YEeckhout LWang Z(2016)A low-cost conflict-free NoC for GPGPUsProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897963(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2897963
Luo HWei SChen DGuo D(2014)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessorsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2014.05.00374:9(2818-2830)Online publication date: 1-Sep-2014
https://dl.acm.org/doi/10.1016/j.jpdc.2014.05.003
Abbas AAli MFayyaz AGhosh AKalra AKhan SKhan MDe Menezes TPattanayak SSanyal AUsman S(2014)A survey on energy-efficient methodologies and architectures of network-on-chipComputers and Electrical Engineering10.1016/j.compeleceng.2014.07.01240:8(333-347)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.compeleceng.2014.07.012
Buckler MBurleson WSadowski GChou PHuang RXie YKarnik T(2013)Low-power networks-on-chipProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648700(132-134)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.5555/2648668.2648700
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