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research-article

Spider: A High-Speed Network Interconnect

Published: 01 January 1997 Publication History

Abstract

The SGI SPIDER chip provides a high-speed, reliable switching network with a flexible interface and topology suitable for a variety of high-end applications. Six full-duplex ports and a nonblocking internal crossbar can sustain a data transfer rate of 4.8 Gbytes/sec, either between chips in a single chassis or between remote chassis over cables up to 5 meters long. Messages of arbitrary length travel over four independent virtual channels with 256 levels of priority, and are protected by CCITT-CRC with hardware retry. These features make the SGI SPIDER well suited to serve as an interprocessor communication fabric, a distributed graphics switch fabric, or a central switch for high-end networking applications.

References

[1]
W. Stallings, Data and Computer Communications, Macmillan Publishing Co., Riverside, N.J., 1988, pp. 137-144.
[2]
W.J. Dally, "Virtual Channel Flow Control," Proc. IEEE 17th Int'l Symp. Computer Architecture, IEEE Computer Soc. Press, Los Alamitos, Calif., 1990, pp. 60-68.
[3]
Y. Tamir and H.-C. Chi, "Symmetric Crossbar Arbiters for VLSI Communication Switches," IEEE Trans. Parallel and Distributed Systems, Vol. 4, No. 1, 1993, pp. 13-27.

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  • (2020)LBNoCACM Transactions on Design Automation of Electronic Systems10.1145/336599425:1(1-26)Online publication date: 15-Jan-2020
  • (2018)FreewayNoCProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306627(1-8)Online publication date: 4-Oct-2018
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Information & Contributors

Information

Published In

cover image IEEE Micro
IEEE Micro  Volume 17, Issue 1
January 1997
75 pages

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 January 1997

Author Tags

  1. SGI Spider chip
  2. Switching networks
  3. interconnects
  4. interprocessor communication

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Cited By

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  • (2022)DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharingWireless Networks10.1007/s11276-021-02882-x28:2(505-520)Online publication date: 1-Feb-2022
  • (2020)LBNoCACM Transactions on Design Automation of Electronic Systems10.1145/336599425:1(1-26)Online publication date: 15-Jan-2020
  • (2018)FreewayNoCProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306627(1-8)Online publication date: 4-Oct-2018
  • (2017)ProNoCMicroprocessors & Microsystems10.1016/j.micpro.2017.08.00754:C(60-74)Online publication date: 1-Oct-2017
  • (2017)BlackOutJournal of Parallel and Distributed Computing10.1016/j.jpdc.2017.01.016104:C(130-145)Online publication date: 1-Jun-2017
  • (2016)Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request NetworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253828424:10(3013-3026)Online publication date: 1-Oct-2016
  • (2015)Low latency network-on-chip router microarchitecture using request masking techniqueInternational Journal of Reconfigurable Computing10.1155/2015/5708362015(2-2)Online publication date: 1-Jan-2015
  • (2015)Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip RoutersACM Transactions on Parallel Computing10.1145/27423492:1(1-23)Online publication date: 21-May-2015
  • (2015)ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on ChipIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.238344223:12(3015-3028)Online publication date: 20-Nov-2015
  • (2015)FreeRider: Non-Local Adaptive Network-on-Chip Routing with Packet-Carried Propagation of Congestion InformationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2014.234506526:8(2272-2285)Online publication date: 1-Aug-2015
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