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Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits

Authors:

Chien-Chih Huang,

Pei-Wen LuoAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19, Issue 1

Article No.: 7, Pages 1 - 13

https://doi.org/10.1145/2534394

Published: 20 December 2013 Publication History

Abstract

Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.

References

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Chen, J.-E., Luo, P.-W., and Wey, C. L. 2010. Placement optimization for yield improvement of switched-capacitor analog integrated circuits. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 29, 2, 313--318.

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Luo, P.-W., Chen, J.-E., Wey, C. L., Cheng, L.-C., Chen, J.-J., and Wu, W.-C. 2008. Impact of capacitance correlation on yield enhancement of mixed-signal/analog integrated circuits. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 27, 11, 2097--2101.

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Cited By

Liu BChen GYang BNakatake S(2018)Routable and Matched Layout Styles for Analog Module GenerationACM Transactions on Design Automation of Electronic Systems10.1145/318216923:4(1-17)Online publication date: 28-Jun-2018
https://dl.acm.org/doi/10.1145/3182169
Huang CChen JWey C(2017)PACESIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256140336:1(134-145)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2561403
Wu PLin MLi XHo T(2016)Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingACM Transactions on Design Automation of Electronic Systems10.1145/285603121:3(1-22)Online publication date: 19-Apr-2016
https://dl.acm.org/doi/10.1145/2856031
Show More Cited By

Index Terms

Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 19, Issue 1

December 2013

210 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2558148

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 20 December 2013

Accepted: 01 July 2013

Revised: 01 May 2013

Received: 01 October 2012

Published in TODAES Volume 19, Issue 1

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Cited By

Liu BChen GYang BNakatake S(2018)Routable and Matched Layout Styles for Analog Module GenerationACM Transactions on Design Automation of Electronic Systems10.1145/318216923:4(1-17)Online publication date: 28-Jun-2018
https://dl.acm.org/doi/10.1145/3182169
Huang CChen JWey C(2017)PACESIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256140336:1(134-145)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2561403
Wu PLin MLi XHo T(2016)Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingACM Transactions on Design Automation of Electronic Systems10.1145/285603121:3(1-22)Online publication date: 19-Apr-2016
https://dl.acm.org/doi/10.1145/2856031
Huang CWey CChen JLuo P(2015)Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCsACM Transactions on Design Automation of Electronic Systems10.1145/277087221:1(1-17)Online publication date: 2-Dec-2015
https://dl.acm.org/doi/10.1145/2770872
Wu PLin MLi XHo TDavoodi AYoung E(2015)Common-Centroid FinFET Placement Considering the Impact of Gate MisalignmentProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717769(25-31)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2717769

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