article

A fully differential comparator-based switched-capacitor ΔΣ modulator

Authors:

Mu-Chen Huang,

Shen-Iuan LiuAuthors Info & Claims

IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 56, Issue 5

Pages 369 - 373

https://doi.org/10.1109/TCSII.2009.2019166

Published: 01 May 2009 Publication History

Abstract

In this brief, a fully differential comparator-based switched-capacitor (CBSC) second-order delta-sigma (ΔΣ) modulator is Presented. To ensure differential operation, the CBSC ΔΣ modulator utilizes a common-mode feedback circuit to balance the pull-up current and the pull-down current in the ramp generator. This modulator has been fabricated in a standard O.18-µm CMOS process. The active area is O.21 mm², and the power consumption, excluding output buffers, is 0.42 mW from a 1.8-V supply. This modulator achieves 65.3-dB signal-to-noise-plus-distortion ratio and an input dynamic range of 71 dB when sampled at 2.56 MS/s (OSR = 64).

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cover image IEEE Transactions on Circuits and Systems II: Express Briefs

IEEE Transactions on Circuits and Systems II: Express Briefs Volume 56, Issue 5

May 2009

87 pages

ISSN:1549-7747

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IEEE Press

Publication History

Published: 01 May 2009

Revised: 03 February 2009

Received: 10 October 2008

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Sun QTu RXie JGong YWu SLi JLuo Z(2024)A rail-to-rail high speed comparator with LVDS output in 0.18-μm SiGe BiCMOS TechnologyIntegration, the VLSI Journal10.1016/j.vlsi.2024.10219897:COnline publication date: 1-Jul-2024
https://dl.acm.org/doi/10.1016/j.vlsi.2024.102198
Carrillo JTorelli GDomínguez MPérez-Aloe RValverde JDuque-Carrillo J(2010)A family of low-voltage bulk-driven CMOS continuous-time CMFB circuitsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2010.206809057:11(863-867)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCSII.2010.2068090

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Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

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