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Closing the smoothness and uniformity gap in area fill synthesis

Published: 07 April 2002 Publication History

Abstract

Control of variability in the back end of the line, and hence in interconnect performance as well, has become extremely difficult with the introduction of new materials such as copper and low-k dielectrics. Uniformity of chemical-mechanical planarization (CMP) requires the addition of area fill geometries into the layout, in order to smoothen the variation of feature densities across the die. Our work addresses the following smoothness gap in the recent literature on area fill synthesis. (1)The very first paper on the filling problem (Kahng et al., ISPD98 [7]) noted that there is potentially a large difference between the optimum window densities in fixed dissections vs. when all possible windows in the layout are considered. (2)Despite this observation, all filling methods since 1998 minimize and evaluate density variation only with respect to a fixed dissection. This paper gives the first evaluation of existing filling algorithms with respect to "gridless" ("floating-window") mode, according to both the effective and spatial density models. Our experiments indicate surprising advantages of Monte-Carlo and greedy strategies over "optimal" linear programming (LP) based methods. Second, we suggest new, more relevant methods of measuring a local uniformity based on Lipschitz conditions, and empirically demonstrate that Monte-Carlo methods are inherently better than LP with respect to the new criteria. Finally, we propose new LP-based filling methods that are directly driven by the new criteria, and show that these methods indeed help close the "smoothness gap".

References

[1]
D. Boning, B. Lee, T. Tubawa, and T. Park, "Models for Pattern Dependencies: Capturing Effects in Oxide, STI, and Copper CMP", Semicon/West Tech. Symp.: CMP Tech. for ULSI Manuf., July 2001.
[2]
Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Hierarchical Dummy Fill for Process Uniformity", Proc. ASP-DAC, Jan. 2001, pp.139--144.
[3]
Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Practical Iterated Fill Synthesis for CMP Uniformity", Proc. Design Automation Conf., Los Angeles, June 2000, pp. 671--674.
[4]
Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "New Monte-Carlo Algorithms for Layout Density Control", Proc. ASP-DAC, 2000, pp. 523--528.
[5]
R. R. Divecha, B. E. Stine, D. O. Ouma, J. U. Yoon, D. S. Boning, et al., "Effect of Fine-line Density and Pitch on Interconnect ILD Thickness Variation in Oxide CMP Process", Proc. CMP-MIC, 1998.
[6]
A. B. Kahng, G. Robins, A. Singh, H. Wang and A. Zelikovsky, "Filling Algorithms and Analyses for Layout Density Control", IEEE Trans. Computer-Aided Design 18(4) (1999), pp. 445--462.
[7]
A. B. Kahng, G. Robins, A. Singh, H. Wang and A. Zelikovsky, "Filling and Slotting: Analysis and Algorithms", Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1998, pp. 95--102.
[8]
G. Nanz and L. E. Camilletti, "Modeling of Chemical-Mechanical Polishing: A Review", IEEE Trans. on Semiconductor Manuf. 8(4) (1995), pp. 382--389.
[9]
D. Ouma, D. Boning, J. Chung, G. Shinn, L. Olsen, and J. Clark, "An Integrated Characterization and Modeling Methodology for CMP Dielectric Planarization", Intl. Interconnect Technology Conference, San Francisco, CA, June 1998.
[10]
B. Stine, "A Closed-Form Analytical Model for ILD Thickness Variation in CMP Processes", Proc. CMP-MIC, 1997.
[11]
B. Stine, D. Ouma, R. Divecha, D. Boning and J. Chung, "Rapid Characterization and Modeling of Pattern Dependent Variation in Chemical Mechanical Polishing", IEEE Trans. Semi. Manuf., Feb. 1998.
[12]
R. Tian, D. Wong, and R. Boone, "Model-Based Dummy Feature Placement for Oxide Chemical Mechanical Polishing Manufacturability", Proc. Design Automation Conf., June 2000, pp. 667--670.
[13]
R. Tian, X. Tang and D. F. Wong, "Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process ", International Symposium on Physical Design, April 2001, pp. 118--123.

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  • (2022)Timing-Aware Fill Insertions With Design-Rule and Density ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385441:10(3529-3542)Online publication date: Oct-2022
  • (2020)Equivalent Capacitance Guided Dummy Fill Insertion for Timing and ManufacturabilityProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045668(133-138)Online publication date: 17-Jan-2020
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Published In

cover image ACM Conferences
ISPD '02: Proceedings of the 2002 international symposium on Physical design
April 2002
216 pages
ISBN:1581134606
DOI:10.1145/505388
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 07 April 2002

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Author Tags

  1. VLSI manufacturability
  2. chemical-mechanical polishing
  3. density analysis
  4. dummy fill problem
  5. monte-carlo

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ISPD02
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ISPD02: International Symposium on Physical Design
April 7 - 10, 2002
CA, San Diego, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

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  • (2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
  • (2022)Timing-Aware Fill Insertions With Design-Rule and Density ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385441:10(3529-3542)Online publication date: Oct-2022
  • (2020)Equivalent Capacitance Guided Dummy Fill Insertion for Timing and ManufacturabilityProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045668(133-138)Online publication date: 17-Jan-2020
  • (2019)FITProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317826(1-6)Online publication date: 2-Jun-2019
  • (2017)High Performance Dummy Fill Insertion With Coupling and Uniformity ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.263845236:9(1532-1544)Online publication date: Sep-2017
  • (2016)Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware DummificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.248849235:4(598-610)Online publication date: Apr-2016
  • (2015)EUV and e-beam manufacturabilityProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2747925(1-6)Online publication date: 7-Jun-2015
  • (2014)Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware DummificationProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593215(1-6)Online publication date: 1-Jun-2014
  • (2014)Simultaneous EUV flare- and CMP-aware placement2014 IEEE 32nd International Conference on Computer Design (ICCD)10.1109/ICCD.2014.6974689(249-255)Online publication date: Oct-2014
  • (2014)Simultaneous EUV flare variation minimization and CMP control with coupling-aware dummification2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)10.1109/DAC.2014.6881381(1-6)Online publication date: Jun-2014
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