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Intel nehalem processor core made FPGA synthesizable

Authors:

Graham Schelle,

Jamison Collins,

Ethan Schuchman,

Gautham Chinya,

Thorsten Mattner,

Per Hammarlund,

Sebastian Steibl,

Hong WangAuthors Info & Claims

FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

Pages 3 - 12

https://doi.org/10.1145/1723112.1723116

Published: 21 February 2010 Publication History

Abstract

We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

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P. H. Wang, J. D. Collins, C. T. Weaver, B. Kuttanna, S. Salamian, G. N. Chinya, E. Schuchman, O. Schilling, T. Doil, S. Steibl, and H. Wang. Intel Atom Processor Core Made FPGA-Synthesizable. In FPGA '09: Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, pages 209--218, New York, NY, USA, 2009. ACM.

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Huang PGuo LSun LZhang X(2022)A Two-Stage Method for Routing in Field-Programmable Gate Arrays with Time-Division MultiplexingTsinghua Science and Technology10.26599/TST.2021.901009227:6(902-911)Online publication date: Dec-2022
https://doi.org/10.26599/TST.2021.9010092
Liu WChen MChang CChang CChang Y(2021)Time-Division Multiplexing Based System-Level FPGA Routing2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643558(1-6)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643558
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Index Terms

Intel nehalem processor core made FPGA synthesizable
1. Computer systems organization
  1. Architectures

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Information & Contributors

Information

Published In

cover image ACM Conferences

FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

February 2010

308 pages

ISBN:9781605589114

DOI:10.1145/1723112

General Chair:
Peter Cheung
Imperial College London, UK
,
Program Chair:
John Wawrzynek
UC Berkeley, USA

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 February 2010

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FPGA '10

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SIGDA

FPGA '10: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 21 - 23, 2010

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Huang PGuo LSun LZhang X(2022)A Two-Stage Method for Routing in Field-Programmable Gate Arrays with Time-Division MultiplexingTsinghua Science and Technology10.26599/TST.2021.901009227:6(902-911)Online publication date: Dec-2022
https://doi.org/10.26599/TST.2021.9010092
Liu WChen MChang CChang CChang Y(2021)Time-Division Multiplexing Based System-Level FPGA Routing2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643558(1-6)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643558
Sun LGuo LHuang P(2021)System-Level FPGA Routing for Logic Verification with Time-Division MultiplexingParallel and Distributed Computing, Applications and Technologies10.1007/978-3-030-69244-5_18(210-218)Online publication date: 21-Feb-2021
https://doi.org/10.1007/978-3-030-69244-5_18
Zou PLin ZShi XWu YChen JYu JChang YLi Z(2020)Time-division multiplexing based system-level FPGA routing for logic verificationProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437551(1-6)Online publication date: 20-Jul-2020
https://dl.acm.org/doi/10.5555/3437539.3437551
Sweeney JMohammed Zackriya VPagliarini SPileggi L(2020)Latch-Based Logic Locking2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HOST45689.2020.9300256(132-141)Online publication date: 7-Dec-2020
https://doi.org/10.1109/HOST45689.2020.9300256
Matthews EGao YShannon L(2020)Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM48280.2020.00025(120-128)Online publication date: May-2020
https://doi.org/10.1109/FCCM48280.2020.00025
Li XMaskell D(2019)Time-Multiplexed FPGA Overlay ArchitecturesACM Transactions on Design Automation of Electronic Systems10.1145/333986124:5(1-19)Online publication date: 23-Jul-2019
https://dl.acm.org/doi/10.1145/3339861
Mashimo SInoue KShioya RFujita AMatsuo RAkaki SFukuda AKoizumi TKadomoto JIrie HGoshima M(2019)An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00016(63-71)Online publication date: Dec-2019
https://doi.org/10.1109/ICFPT47387.2019.00016
Khan FYe A(2018)An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA ArchitecturesACM Transactions on Reconfigurable Technology and Systems10.1145/318239411:1(1-23)Online publication date: 14-Mar-2018
https://dl.acm.org/doi/10.1145/3182394
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