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On optimal board-level routing for FPGA-based logic emulation

Authors:

Wai-Kei Mak,

D. F. WongAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 552 - 556

https://doi.org/10.1145/217474.217586

Published: 01 January 1995 Publication History

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W.K. Mak, and D.F. Wong, On Optimal Board-Level Routing for FPGA-based Logic Emulation, Technical Report, TR94-30, Department of Computer Sciences, University of Texas at Austin, 1994.

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Cited By

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Schelle GCollins JSchuchman EWang PZou XChinya GPlate RMattner TOlbrich FHammarlund PSinghal RBrayton JSteibl SWang HCheung PWawrzynek J(2010)Intel nehalem processor core made FPGA synthesizableProceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723116(3-12)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723116
Hauck SBorriello G(2006)Pin assignment for multi-FPGA systemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.65856416:9(956-964)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.658564
Lin SLin YHwang T(2006)Net assignment for the FPGA-based logic emulation system in the folded-Clos network structureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.59483716:3(316-320)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.594837
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Index Terms

On optimal board-level routing for FPGA-based logic emulation
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design
    1. Application-specific VLSI designs
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 January 1995

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June 12 - 16, 1995

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Schelle GCollins JSchuchman EWang PZou XChinya GPlate RMattner TOlbrich FHammarlund PSinghal RBrayton JSteibl SWang HCheung PWawrzynek J(2010)Intel nehalem processor core made FPGA synthesizableProceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723116(3-12)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723116
Hauck SBorriello G(2006)Pin assignment for multi-FPGA systemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.65856416:9(956-964)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.658564
Lin SLin YHwang T(2006)Net assignment for the FPGA-based logic emulation system in the folded-Clos network structureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.59483716:3(316-320)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.594837
Srinivasan VRadhakrishnan SVemuri RWalrath J(2006)Interconnect synthesis for reconfigurable multi-FPGA architecturesParallel and Distributed Processing10.1007/BFb0097943(588-596)Online publication date: 28-Oct-2006
https://doi.org/10.1007/BFb0097943
Ejnioui ARanganathan N(2003)Multiterminal net routing for partial crossbar-based multi-FPGA systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80052311:1(71-78)Online publication date: 1-Feb-2003
https://dl.acm.org/doi/10.1109/TVLSI.2002.800523
Jain SKumar AKumar S(2003)Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop RoutingDesign Automation for Embedded Systems10.1023/B:DAEM.0000013065.87652.df8:4(309-326)Online publication date: 1-Dec-2003
https://dl.acm.org/doi/10.1023/B%3ADAEM.0000013065.87652.df
Jain SKumar AKumar S(2002)Hybrid Multi-FPGA board evaluation by limiting multi-hop routingProceedings 13th IEEE International Workshop on Rapid System Prototyping10.1109/IWRSP.2002.1029740(66-73)Online publication date: 2002
https://doi.org/10.1109/IWRSP.2002.1029740
Vemuri RGovindarajan SOuaiss IKaul MSrinivasan VRadhakrishnan SSundaraman SGanesan SPandey ALakshmikanthan P(2001)Automated design synthesis and partitioning for adaptive reconfigurable hardwareHardware implementation of intelligent systems10.5555/570780.570781(3-52)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.5555/570780.570781
Chen CLiu CHwang T(2001)Architecture driven circuit partitioningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.9240609:2(383-390)Online publication date: 1-Apr-2001
https://dl.acm.org/doi/10.1109/92.924060
Vemuri RGovindarajan SOuaiss IKaul MSrinivasan VRadhakrishnan SSundaraman SGanesan SPandey ALakshmikanthan P(2001)Automated Design Synthesis and Partitioning for Adaptive Reconfigurable HardwareHardware Implementation of Intelligent Systems10.1007/978-3-7908-1816-1_1(3-52)Online publication date: 2001
https://doi.org/10.1007/978-3-7908-1816-1_1
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On optimal board-level routing for FPGA-based logic emulation

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