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Integrating Online and Offline Testing of a Switching Memory

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Matteo Sonza ReordaAuthors Info & Claims

IEEE Design & Test, Volume 15, Issue 1

Pages 63 - 70

https://doi.org/10.1109/54.655184

Published: 01 January 1998 Publication History

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Abstract

The article describes the architecture of a circuit used in a telephone switching unit and focuses on its on-line and off-line test features. Several techniques have been exploited: BIST is adopted to test some embedded memories, Partial Scan allows the test of the remaining logic, and Boundary Scan is used to activate the test and gather the results. Data are reported, concerning the obtained fault coverage, the hardware overhead and the performance penalties introduced by the approach. By sharing the same circuitry for both on-line and off-line testing we succeeded in minimizing the additional logic.

References

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P. Camurati, et al., "Industrial BIST of Embedded RAMs," IEEE Design & Test of Computers, Vol. 12, No. 3, Fall 1995, pp. 86-95.

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Hellebrand SWunderlich HIvaniuk AKlimets YYarmolik V(2002)Efficient Online and Offline Testing of Embedded DRAMsIEEE Transactions on Computers10.1109/TC.2002.101770051:7(801-809)Online publication date: 1-Jul-2002
https://dl.acm.org/doi/10.1109/TC.2002.1017700
Hellebrand SWunderlich HIvaniuk AKlimets YYarmolik V(1999)Error Detecting Refreshment for Embedded DRAMsProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836539Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836539
Lobetti-Bondoni MPricco ABenso AChiusano SPrinetto P(1999)An On-Line BISTed SRAM IP CoreProceedings of the 1999 IEEE International Test Conference10.5555/518925.939385Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939385

Integrating Online and Offline Testing of a Switching Memory
1. Computer systems organization
2. Hardware

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Published In

IEEE Design & Test Volume 15, Issue 1

January 1998

88 pages

ISSN:0740-7475

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 January 1998

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Hellebrand SWunderlich HIvaniuk AKlimets YYarmolik V(2002)Efficient Online and Offline Testing of Embedded DRAMsIEEE Transactions on Computers10.1109/TC.2002.101770051:7(801-809)Online publication date: 1-Jul-2002
https://dl.acm.org/doi/10.1109/TC.2002.1017700
Hellebrand SWunderlich HIvaniuk AKlimets YYarmolik V(1999)Error Detecting Refreshment for Embedded DRAMsProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836539Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836539
Lobetti-Bondoni MPricco ABenso AChiusano SPrinetto P(1999)An On-Line BISTed SRAM IP CoreProceedings of the 1999 IEEE International Test Conference10.5555/518925.939385Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939385

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Incorporating I_DDQ Testing with BIST forImproved Coverage: An Experimental Study

On automatic generation of RTL validation test benches using circuit testing techniques

An Effective BIST Scheme for ROM's

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