Article

Transparent BIST for RAMs

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Michael NicolaidisAuthors Info & Claims

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design

Pages 598 - 607

Published: 20 September 1992 Publication History

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Li JTseng TWey C(2005)An Efficient Transparent Test Scheme for Embedded Word-Oriented MemoriesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.56(574-579)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.56
Hellebrand SWunderlich HIvaniuk AKlimets YYarmolik V(2002)Efficient Online and Offline Testing of Embedded DRAMsIEEE Transactions on Computers10.1109/TC.2002.101770051:7(801-809)Online publication date: 1-Jul-2002
https://dl.acm.org/doi/10.1109/TC.2002.1017700
Thaller K(2001)A Highly-Efficient Transparent Online Memory TestProceedings of the 2001 IEEE International Test Conference10.5555/839296.843825Online publication date: 30-Oct-2001
https://dl.acm.org/doi/10.5555/839296.843825
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Theory of Transparent BIST for RAMs

In this paper I present the theoretical aspects of a technique called transparent BIST for RAMs. This technique applies to any RAM test algorithm and transforms it into a transparent one. The interest of the transparent test algorithms is that testing ...
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Previous studies show that intra-cluster communication easily becomes a major performance bottleneck for a wide range of small write-sharing workloads especially read-only workloads in modern clustered network servers. A Remote Direct Memory Access (...

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Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design

September 1992

971 pages

ISBN:0780307607

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IEEE Computer Society

United States

Publication History

Published: 20 September 1992

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Li JTseng TWey C(2005)An Efficient Transparent Test Scheme for Embedded Word-Oriented MemoriesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.56(574-579)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.56
Hellebrand SWunderlich HIvaniuk AKlimets YYarmolik V(2002)Efficient Online and Offline Testing of Embedded DRAMsIEEE Transactions on Computers10.1109/TC.2002.101770051:7(801-809)Online publication date: 1-Jul-2002
https://dl.acm.org/doi/10.1109/TC.2002.1017700
Thaller K(2001)A Highly-Efficient Transparent Online Memory TestProceedings of the 2001 IEEE International Test Conference10.5555/839296.843825Online publication date: 30-Oct-2001
https://dl.acm.org/doi/10.5555/839296.843825
Hellebrand SWunderlich HIvaniuk AKlimets YYarmolik V(1999)Error Detecting Refreshment for Embedded DRAMsProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836539Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836539
Zarrineh KUpadhyaya S(1999)On programmable memory built-in self test architecturesProceedings of the conference on Design, automation and test in Europe10.1145/307418.307593(136-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307593
Hellebrand SWunderlich HYarmolik V(1999)Symmetric transparent BIST for RAMsProceedings of the conference on Design, automation and test in Europe10.1145/307418.307592(135-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307592
Yarmolik VHellebrand SWunderlich HDewilde PRammig FMusgrave G(1998)Self-adjusting output data compressionProceedings of the conference on Design, automation and test in Europe10.5555/368058.368129(173-179)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368129
Zhao WPapachristou CDewilde PRammig FMusgrave G(1998)Testing DSP cores based on self-test programsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368128(166-172)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368128
Barbagallo SMedina DCorno FPrinetto PReorda M(1998)Integrating Online and Offline Testing of a Switching MemoryIEEE Design & Test10.1109/54.65518415:1(63-70)Online publication date: 1-Jan-1998
https://dl.acm.org/doi/10.1109/54.655184
Nicolaidis M(1996)Theory of Transparent BIST for RAMsIEEE Transactions on Computers10.1109/12.54370845:10(1141-1156)Online publication date: 1-Oct-1996
https://dl.acm.org/doi/10.1109/12.543708
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Theory of Transparent BIST for RAMs

Built-In Self-Test for Multi-Port RAMs

RAMS: a RDMA-enabled I/O cache architecture for clustered network servers

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