research-article

Conquering Noise in Deep-Submicron Digital ICs

Authors:

Kenneth L. Shepard,

Vinod NarayananAuthors Info & Claims

IEEE Design & Test, Volume 15, Issue 1

Pages 51 - 62

https://doi.org/10.1109/54.655183

Published: 01 January 1998 Publication History

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Abstract

Design methodologies for digital integrated circuits are ultimately concerned with validating a design against metrics which ensure functionality, testability, and that the design satisfies power and timing requirements. Electronic design automation (EDA) tools and techniques have been developed to analyze each of these metrics. With technology scaling and increasing clock frequencies, noise and signal integrity are becoming important new design concerns in verifying functionality and accurately predicting timing. In this article, we describe a new metric for verifying functionality in the presence of noise, noise stability, and a static noise analysis methodology to verify it. In addition, we describe the effects of noise on delay and how these can be considered in the context of static timing analysis.

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Cited By

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Lau MLing KChu YHenkel JParameswaran S(2009)Energy-aware probabilistic multiplierProceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1629395.1629434(281-290)Online publication date: 11-Oct-2009
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Chakrapani LAkgul BCheemalavagu SKorkmaz PPalem KSeshasayee BGielen G(2006)Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technologyProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131790(1110-1115)Online publication date: 6-Mar-2006
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George JMarr BAkgul BPalem KHong SWolf WFlautner KKim T(2006)Probabilistic arithmetic and energy efficient embedded signal processingProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176781(158-168)Online publication date: 22-Oct-2006
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Conquering Noise in Deep-Submicron Digital ICs
1. Hardware
  1. Electronic design automation

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Published In

IEEE Design & Test Volume 15, Issue 1

January 1998

88 pages

ISSN:0740-7475

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 January 1998

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Lau MLing KChu YHenkel JParameswaran S(2009)Energy-aware probabilistic multiplierProceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1629395.1629434(281-290)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629395.1629434
Chakrapani LAkgul BCheemalavagu SKorkmaz PPalem KSeshasayee BGielen G(2006)Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technologyProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131790(1110-1115)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131790
George JMarr BAkgul BPalem KHong SWolf WFlautner KKim T(2006)Probabilistic arithmetic and energy efficient embedded signal processingProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176781(158-168)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176760.1176781
Gyure AKasnavi ALo STehrani PShu WShahram MWang JZedja J(2005)Noise Library Characterization for Large Capacity Static Noise Analysis ToolsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.85(28-34)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.85
Shanbhag N(2004)Reliable and Efficient System-on-Chip DesignComputer10.1109/MC.2004.127400337:3(42-50)Online publication date: 1-Mar-2004
https://dl.acm.org/doi/10.1109/MC.2004.1274003
Kasnavi AWang JShahram MZejda J(2004)Analytical modeling of crosstalk noise waveforms using Weibull functionProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382561(141-146)Online publication date: 7-Nov-2004
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Milter OKolodny A(2003)Crosstalk noise reduction in synthesized digital logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81755111:6(1153-1158)Online publication date: 1-Dec-2003
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Bergamaschi RCohn JPileggi LKuehlmann A(2002)The A to Z of SoCsProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774689(790-798)Online publication date: 10-Nov-2002
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Shanbhag NAckland B(2002)Reliable and energy-efficient digital signal processingProceedings of the 39th annual Design Automation Conference10.1145/513918.514124(830-835)Online publication date: 10-Jun-2002
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Xiao TMarek-Sadowska MRabaey J(2001)Functional correlation analysis in crosstalk induced critical paths identificationProceedings of the 38th annual Design Automation Conference10.1145/378239.379041(653-656)Online publication date: 22-Jun-2001
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Noise in deep submicron digital design

Intrinsic leakage in deep submicron CMOS ICs—measurement-based test solutions

Estimation of the defective IDDQ caused by shorts in deep-submicron CMOS ICs

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