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A low power video processor

Authors:

Uzi Zangi,

Ran GinosarAuthors Info & Claims

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

Pages 136 - 138

https://doi.org/10.1145/280756.280835

Published: 10 August 1998 Publication History

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Abstract

Multiple power saving methods were applied to a video processor for color digital video and still cameras. Architectural level methods failed to save power: asynchronous design, dynamic voltage scaling, bus switching minimization, pipeline stage merging, reduction of switching times and clock gating. However changing the algorithm to work on pixel differences yielded 3-15% power reduction in typical cases.

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Cited By

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Silpa BPatney AKrishna TPanda PVisweswaran GNassif SRoychowdhury J(2008)Texture filter memoryProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509581(559-564)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509581
Choi BLee D(2003)Frequent Value Cache for Low-Power Asynchronous Dual-Rail BusIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-39762-5_58(520-529)Online publication date: 2003
https://doi.org/10.1007/978-3-540-39762-5_58

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A low power video processor

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Information

Published In

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

August 1998

318 pages

ISBN:1581130597

DOI:10.1145/280756

Chairmen:
Anantha Chandrakasan
MIT
,
Sayfe Kiaei
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 August 1998

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ISLPED98

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IEEE-EDS
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IEEE-SSCS
IEEE-CAS

ISLPED98: International Symposium on Low Power Electronics and Design

August 10 - 12, 1998

California, Monterey, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Silpa BPatney AKrishna TPanda PVisweswaran GNassif SRoychowdhury J(2008)Texture filter memoryProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509581(559-564)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509581
Choi BLee D(2003)Frequent Value Cache for Low-Power Asynchronous Dual-Rail BusIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-39762-5_58(520-529)Online publication date: 2003
https://doi.org/10.1007/978-3-540-39762-5_58

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Recommendations

LOW-POWER PROCESSOR DESIGN

Cell Processor Low-Power Design Methodology

Power-Aware Processor System Design