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research-article

On-chip decoupling capacitor optimization using architectural level prediction

Authors:

Mondira Deb Pant,

Donald Scott WillsAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 10, Issue 3

Pages 319 - 326

https://doi.org/10.1109/TVLSI.2002.1043335

Published: 01 June 2002 Publication History

Abstract

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.

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Cited By

Sadat SCanbolat MKöse S(2018)Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power GridACM Transactions on Design Automation of Electronic Systems10.1145/317787723:4(1-15)Online publication date: 9-May-2018
https://dl.acm.org/doi/10.1145/3177877
Pathak DSavidis I(2018)On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction VaractorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285608726:11(2230-2240)Online publication date: 1-Nov-2018
https://dl.acm.org/doi/10.1109/TVLSI.2018.2856087
Bai YSong YBojnordi MShapiro AFriedman EIpek E(2016)Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.245587424:4(1266-1279)Online publication date: 21-Mar-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2455874
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Index Terms

On-chip decoupling capacitor optimization using architectural level prediction
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
    2. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Very large scale integration design
    1. VLSI system specification and constraints

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 10, Issue 3

June 2002

182 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 2002.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 June 2002

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Cited By

Sadat SCanbolat MKöse S(2018)Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power GridACM Transactions on Design Automation of Electronic Systems10.1145/317787723:4(1-15)Online publication date: 9-May-2018
https://dl.acm.org/doi/10.1145/3177877
Pathak DSavidis I(2018)On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction VaractorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285608726:11(2230-2240)Online publication date: 1-Nov-2018
https://dl.acm.org/doi/10.1109/TVLSI.2018.2856087
Bai YSong YBojnordi MShapiro AFriedman EIpek E(2016)Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.245587424:4(1266-1279)Online publication date: 21-Mar-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2455874
Xuan Wang Jiang Xu Wei Zhang Xiaowen Wu Yaoyao Ye Zhehui Wang Nikdast MZhe Wang (2015)Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.230695923:2(266-279)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2306959
(2015)Analyzing the codeIEEE Spectrum10.1109/MSPEC.2015.711556652:6(50-51)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1109/MSPEC.2015.7115566
Ogasahara YHashimoto MKanamoto TOnoye T(2013)Supply noise suppression by triple-well structureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219245821:4(781-785)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2192458
Rius J(2013)IR-drop in on-chip power distribution networks of ICs with nonuniform power consumptionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218891821:3(512-522)Online publication date: 1-Mar-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2188918
Hu XCondley WGuthaus MGroeneveld PSciuto DHassoun S(2012)Library-aware resonant clock synthesis (LARCS)Proceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228389(145-150)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228389
Ahmad WChen QZheng LTenhunen H(2012)Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairsAnalog Integrated Circuits and Signal Processing10.1007/s10470-011-9797-073:1(311-328)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1007/s10470-011-9797-0
Zhang WZhang LShayan AYu WHu XZhu ZEngin ECheng CLin Y(2010)On-chip power network optimization with decoupling capacitors and controlled-ESRsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899747(119-124)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899747
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