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Hierarchical analysis of power distribution networks

Published: 01 June 2000 Publication History

Abstract

Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated through the analysis of case studies of several multi-million node power grids, extracted from real microprocessor and DSP designs.

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Cited By

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  • (2024)Hybrid Model-Based Thermal Analysis Methodology for Integrated Circuits2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617791(637-641)Online publication date: 10-May-2024
  • (2023)Worst-case Power Integrity Prediction Using Convolutional Neural NetworkACM Transactions on Design Automation of Electronic Systems10.1145/356493228:4(1-19)Online publication date: 17-May-2023
  • (2023)An Effective Parallel Acceleration Method for Transient Simulation of Large-Scale Power Ground Network2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218570(29-34)Online publication date: 8-May-2023
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cover image ACM Conferences
DAC '00: Proceedings of the 37th Annual Design Automation Conference
June 2000
819 pages
ISBN:1581131879
DOI:10.1145/337292
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2000

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DAC00: ACM/IEEE-CAS/EDAC Design Automation Conference
June 5 - 9, 2000
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Cited By

View all
  • (2024)Hybrid Model-Based Thermal Analysis Methodology for Integrated Circuits2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617791(637-641)Online publication date: 10-May-2024
  • (2023)Worst-case Power Integrity Prediction Using Convolutional Neural NetworkACM Transactions on Design Automation of Electronic Systems10.1145/356493228:4(1-19)Online publication date: 17-May-2023
  • (2023)An Effective Parallel Acceleration Method for Transient Simulation of Large-Scale Power Ground Network2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218570(29-34)Online publication date: 8-May-2023
  • (2023)Sparse-HeteroCL: From Sparse Tensor Algebra to Highly Customized Accelerators on FPGAs2023 IEEE/ACM 23rd International Symposium on Cluster, Cloud and Internet Computing Workshops (CCGridW)10.1109/CCGridW59191.2023.00061(290-292)Online publication date: May-2023
  • (2019)A CAD approach for suppression of power supply noise and performance analysis of some multi-core processors in pre-layout stageMicrosystem Technologies10.1007/s00542-018-4043-725:5(1977-1986)Online publication date: 1-May-2019
  • (2018)Post-layout Power Supply Noise Suppression and Performance Analysis of Multi-core Processor Using 90 nm Process TechnologyCommunication, Devices, and Computing10.1007/978-981-10-8585-7_19(199-205)Online publication date: 8-Apr-2018
  • (2014)An efficient spectral graph sparsification approach to scalable reduction of large flip-chip power gridsProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691410(218-223)Online publication date: 3-Nov-2014
  • (2014)Incremental Analysis of Power Grids Using Backward Random WalksACM Transactions on Design Automation of Electronic Systems10.1145/261176319:3(1-29)Online publication date: 23-Jun-2014
  • (2013)Placement optimization of power supply pads based on localityProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485681(1655-1660)Online publication date: 18-Mar-2013
  • (2012)PowerRushProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429526(653-659)Online publication date: 5-Nov-2012
  • Show More Cited By

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