Crosstalk-glitch gating: a solution for designing glitch-tolerant asynchronous handshake interface mechanisms for GALS systems
Pages 2696 - 2707
Abstract
This paper proposes a novel solution to make asynchronous handshake interfaces tolerant to crosstalk-glitch propagation (GP). This study leverages our recently proposed crosstalk-glitch modeling technique for asynchronous systems, which models the crosstalk GP in asynchronous interfaces. In this paper, a novel set of solutions to quench the GP is proposed. This set of solutions is called crosstalk-glitch gating, as the quenching is obtained by using carefully generated control signals. A step-by-step method is recommended to apply crosstalk-glitch gating to conventional asynchronous handshake interfaces. Transistor-level electrical simulations demonstrate that our method effectively generates crosstalk-glitch gate-controlling signals. In comparison with contemporary signal-integrity management techniques, our gating methodology can be applied to fewer nodes and earlier in the design cycle.
References
[1]
Semiconductor Industry Association, International Technology Roadmap for Semiconductors 2007.
[2]
B. P. Wong, A. Mittal, Y. Cao, and G. Starr, Nano-CMOS Circuit and Physical Design. New York: Wiley-Interscience, 2005.
[3]
N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuit and Systems Perspective, 3rd ed. Reading, MA: Addison-Wesley, 2004.
[4]
"STMicroelectronics Design Manual for CMOS 90-nm Technology," STMicroelectronics, Geneva, Switzerland, 2005.
[5]
W. J. Bainbridge and S. B. Fuber, "Delay insensitive system-on-chip interconnect using 1-of-4-data encoding," in Proc. 7th Int. Symp. ASYNC, Apr. 2001, pp. 118-126.
[6]
E. G. Jung, B. S. Choi, Y. G. Won, and D. I. Lee, "Handshake protocol using return-to-zero data encoding for high performance asynchronous bus," Proc. Inst. Elect. Eng.--Comput. Digit. Tech., vol. 150, no. 4, pp. 245-251, Jul. 2003.
[7]
E. G. Jung, J. G. Lee, K. S. Jhang, and D. S. Har, "Differential value encoding for delay insensitive handshake protocol," IEICE Trans. Inf. Syst., vol. E88, no. 7, pp. 1437-1444, Jul. 2005.
[8]
S. R. Hasan and Y. Savaria, "Crosstalk effects in event-driven self-timed circuits designed with 90-nm CMOS technology," in Proc. IEEE ISCAS, May 2007, pp. 629-632.
[9]
J. Muttersbach, T. Villiger, and W. Fichtner, "Practical design of globally-asynchronous locally-synchronous systems," in Proc. 6th Int. Symp. ASYNC, Apr. 2000, pp. 52-59.
[10]
H. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addiston-Wesley, 1990.
[11]
Sparsö and S. Furber, Principles of Asynchronous Circuit Design. Boston, MA: Kluwer, 2001.
[12]
K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: Part I (Specification and hazard-free implementations)," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 2, pp. 101-117, Feb. 1999.
[13]
K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: Part II (Automatic synthesis)," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 2, pp. 118-132, Feb. 1999.
[14]
J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits; A Design Perspective, ser. Prentice Hall Electronics and VLSI Series, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2003.
[15]
W. J. Bainbridge, W. B. Toms, D. A. Edwards, and S. B. Furber, "Delay-insensitive, point-to-point interconnect using m-of-n codes," in Proc. 9th Int. Symp. ASYNC, May 2003, pp. 132-140.
[16]
D. Chapiro, "Globally-asynchronous locally-synchronous systems," Ph.D. dissertation, Stanford Univ., Stanford, CA, Oct. 1984.
[17]
M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Designs. Piscataway, NJ: IEEE Press, 1990.
[18]
J. P. Roth, "Diagnosis of automata failures: A calculus and a method," IBM J. Res. Develop., vol. 10, no. 4, pp. 278-291, Jul. 1966.
[19]
K. S. Chung, T. Kim, and C. L. Liu, "G-vector: A new model for glitch analysis in logic circuits," J. VLSI Signal Process. Syst. Signal, Image, Video Technol., vol. 27, no. 3, pp. 235-251, Mar. 2001.
[20]
L. Hyungwoo, S. Hakgun, and K. Juho, "Glitch elimination by gate freezing, gate sizing and buffer insertion for low power optimization circuit," in Proc. IEEE IECON, Nov. 2004, vol. 3, pp. 2126-2131.
[21]
S. R. Hasan, N. Bélanger, Y. Savaria, and O. Ahmad, "Crosstalk glitch propagation modeling for asynchronous handshake schemes in GALS," IEEE Trans. Circuits Syst. I, Reg. Papers, to be published.
[22]
K. Golshan, Physical Design Essentials: An ASIC Design Implementation Perspective. Berlin, Germany: Springer-Verlag, 2006.
[23]
R. B. Lin, "Inter-wire coupling reduction analysis of bus-invert coding," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 7, pp. 1911-1920, Aug. 2008.
[24]
M. R. Becer, D. Blaauw, V. Zolotov, R. Panda, and I. N. Hajj, "Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model," in Proc. DATE, 2002, pp. 456-463.
[25]
R. Manohar and A. J. Martin, Quasi-Delay-Insensitive Circuits Are Turing-Complete California Inst. Technol., Pasadena, CA, Tech. Rep. 00000240, 1995.
[26]
C. S. D'Alessandro, A. Delong Shang Bystrov, A. V. Yakovlev, and O. Maevsky, "Phase-encoding for on-chip signalling," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp. 535-545, Mar. 2008.
[27]
R. B. Lin, "Inter-wire coupling reduction analysis of bus-invert coding," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 7, pp. 1911-1920, Aug. 2008.
[28]
B. Fu and P. Ampadu, "On hamming product codes with type-II hybrid ARQ for on-chip interconnects," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 2042-2054, Sep. 2009.
[29]
F. Wang and V. D. Agrawal, "Single event upset: An embedded tutorial," in Proc. 21st Int. Conf. VLSI Des., Aug. 2008, pp. 429-434.
[30]
C. LaFrieda and R. Manohar, "Fault detection and isolation techniques for quasi delay-insensitive circuits," in Proc. IEEE Int. Conf. Dependable Syst. Netw., 2004, pp. 41-50.
[31]
W. Jang and A. J. Martin, "SEU-tolerant QDI circuits {quasi delay-insensitive asynchronous circuits}," in Proc. 11th Int. Symp. ASYNC, 2005, pp. 156-165.
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Publication History
Published: 01 October 2010
Accepted: 22 February 2010
Revised: 17 January 2010
Received: 28 August 2009
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