More Web Proxy on the site http://driver.im/

research-article

High-level synthesis for designing multimode architectures

Authors:

Caaliph Andriamisaina,

Philippe Coussy,

Emmanuel Casseau,

Cyrille ChavetAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Issue 11

Pages 1736 - 1749

https://doi.org/10.1109/TCAD.2010.2062751

Published: 01 November 2010 Publication History

Abstract

This paper addresses the design of multimode architectures for digital signal and image processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single register transfer level hardware architecture optimized in area is generated. In order to reduce the register, the steering logic, and the controller complexities, this paper proposes a joint-scheduling algorithm, which maximizes the similarities between the control steps and specific binding approaches for both operators and storage elements which maximize the similarities between the datapaths. It is shown through a set of test cases that the proposed approach offers significant area saving and low-performance penalties compared to both state-of-the-art techniques and dedicated mono-mode architectures.

References

[1]

L. Chiou, S. Bhunia, and K. Roy, "Synthesis of application-specific highly efficient multi-mode cores for embedded systems," ACM Trans. Embedded Comput. Syst., vol. 4, no. 1, pp. 168-188, Feb. 2005.

Digital Library

[2]

C. Zhan, S. Khawam, and T. Arslan, "Domain specific reconfigurable fabric targeting Viterbi algorithm," in Proc. IEEE Field-Programmable Technol., 2004, pp. 363-366.

[3]

J. G. Cousin, O. Sentieys, and D. Chillet, "Multi-algorithm ASIP synthesis and power estimation for DSP applications," in Proc. IEEE ISCAS, vol. 2. May 2000, pp. 621-624.

[4]

GAUT: High-Level Synthesis Tool from C to RTL {Online}. Available: http://www-labsticc.univ-ubs.fr/www-gaut

[5]

I. Krikidis, J. L. Danger, and L. Naviner, "An iterative reconfigurability approach for WCDMA high-data-rate communications," IEEE Wirel. Commun., vol. 13, no. 3, pp. 8-14, Jun. 2006.

Digital Library

[6]

E. Piriou, C. Jego, P. Adde, and M. Jezequel, "A flexible architecture for block turbo decoders using BCH or Reed-Solomon components codes," in Proc. IEEE ISVLSI, Mar. 2006, p. 2.

Digital Library

[7]

M. A. Bickerstaff, D. Garrett, T. Prokop, C. Thomas, B. Widdup, G. Zhou, L. M. Davis, G. Woodward, C. Nicol, and R. Yan, "A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18 µm CMOS," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1555-1564, Nov. 2002.

[8]

P. Coussy and A. Morawiec, High-Level Synthesis: From Algorithm to Digital Circuit. Berlin, Germany: Springer, 2008.

Digital Library

[9]

P. Coussy, C. Chavet, P. Bomel, D. Heller, E. Senn, and E. Martin, GAUT: A High-Level Synthesis Tool for DSP Applications. Berlin, Germany: Springer, 2008.

[10]

P. Coussy and A. Takach, "Raising the abstraction level of hardware design," IEEE Des. Test Comput., vol. 26, no. 4, pp. 4-6, Jul.-Aug. 2009.

Digital Library

[11]

A. van der Werf, M. J. H. Peek, E. H. L. Aarts, J. L. Van Meerbergen, P. E. R. Lippens, and W. F. J. Verhaegh, "Area optimization of multifunctional processing units," in Proc. IEEE/ACM ICCAD, 1992, pp. 292- 299.

Digital Library

[12]

W. Geurts, F. Catthoor, and H. De Man, "Quadratic zero-one programming-based synthesis of application-specific data paths," in Proc. IEEE/ACM ICCAD, vol. 14. Jan. 1993, pp. 1-11.

Digital Library

[13]

N. Moreano, E. Borin, C. de Souza, and G. Araujo, "Efficient datapath merging for partially reconfigurable architectures," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 7, pp. 969-980, Jul. 2005.

Digital Library

[14]

K. Fan, M. Kudlur, H. Park, and S. Mahlke, "Increasing hardware efficiency with multifunction loop accelerators," in Proc. Int. Conf. Hardw.-Softw. Codesign Syst. Synt. (CODESS+ISSS), Oct. 2006, pp. 276-281.

Digital Library

[15]

V. V. Kumar and J. Lach, "Highly flexible multi-mode system synthesis," in Proc. Int. Conf. Hardware-Software Codesign Syst. Synt. (CODESS+ISSS), 2005, pp. 27-32.

Digital Library

[16]

C. Huang, Y. Chen, Y. Lin, and Y. Hsu, "Data path allocation based on bipartite weighted matching," in Proc. DAC, 1990, pp. 499-504.

Digital Library

[17]

Z. Huang, S. Malik, N. Moreano, and G. Araujo, "The design of dynamically reconfigurable datapath coprocessors," ACM Trans. Emb. Comput. Syst., vol. 3, no. 2, pp. 361-384, May 2004.

Digital Library

[18]

C. Chavet, C. Andriamisaina, P. Coussy, E. Casseau, E. Juin, P. Urard, and E. Martin, "A design flow dedicated to multimode architectures for DSP applications," in Proc. IEEE/ACM ICCAD, 2007, pp. 604-611.

Digital Library

[19]

G. De Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.

Digital Library

[20]

D. D. Gajski, N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design. Boston, MA: Kluwer, 1992.

Digital Library

[21]

Z. Galil, "Efficient algorithms for finding maximum matching in graphs," ACM Comput. Survey, vol. 18, no. 1, pp. 23-38, 1986.

Digital Library

[22]

B. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning graphs," Bell Syst. Tech. J., vol. 49, pp. 291-308, Feb. 1970.

[23]

A. Hashimoto and J. Stevens, "Wire routing by optimizing channel assignment within large apertures," in Proc. Des. Autom. Workshop, 1971, pp. 155-169.

Digital Library

[24]

P. Bomel, E. Martin, and E. Boutillon, "Synchronization processor synthesis for latency insensitive systems," in Proc. IEEE Int. Conf. DATE, 2005, pp. 896-897.

Digital Library

[25]

A. Bogliolo, L. Benini, and G. De Micheli, "Adaptive least mean square behavioral power modeling," in Proc. DATE, 1997, p. 404.

Digital Library

[26]

M. Frigo and S. G. Johnson, "FFTW: An adaptive software architecture for the FFT," in Proc. IEEE ICASSP, 1998, pp. 1381-1384.

[27]

C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "MediaBench: A tool for evaluating and synthesizing multimedia and communications systems," in Proc. 30th Ann. Int. Symp. Microarchitecture, 1997, pp. 330-335.

Digital Library

[28]

J. G. Proakis and D. G. Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications. Englewood Cliffs, NJ: Prentice-Hall, 1996.

Digital Library

Cited By

Kilic AMarrakchi ZMehrez H(2018)A top-down optimization methodology for mutually exclusive applicationsInternational Journal of Reconfigurable Computing10.1155/2014/8276132014(3-3)Online publication date: 13-Dec-2018
https://dl.acm.org/doi/10.1155/2014/827613
Briki AChavet CCoussy PMartin EBrunvard EStevens KCavallaro JZhang T(2012)A design approach dedicated to network-based and conflict-free parallel interleaversProceedings of the great lakes symposium on VLSI10.1145/2206781.2206819(153-158)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206819

Recommendations

High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective

High-level test synthesis is a special class of high-level synthesis having testability as one of the important components. This article presents a detailed survey on recent developments in high-level test synthesis from a synthesis process flow ...
Automatic correction of RTL designs using a lightweight partial high level synthesis
Abstract
Correction of the digital designs have emerged as a major bottleneck at Register Transfer Level (RTL) due to the growing complexity of the digital systems and shortening time-to-market. Existing automated correction methods face ...
Highlights
- A lightweight partial high level synthesis mechanism to correct RTL designs.
- ...
Stability-based algorithms for high-level synthesis of digital ASICs

This paper presents new algorithms for the scheduling and allocation phases in high-level synthesis under time and resource constraints. This is achieved by formulating these problems in terms of Liapunov's stability theorem using a transformation ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 29, Issue 11

November 2010

191 pages

ISSN:0278-0070

Issue’s Table of Contents

Copyright © 2010.

Publisher

IEEE Press

Publication History

Published: 01 November 2010

Accepted: 24 June 2010

Revised: 19 March 2010

Received: 18 November 2009

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Kilic AMarrakchi ZMehrez H(2018)A top-down optimization methodology for mutually exclusive applicationsInternational Journal of Reconfigurable Computing10.1155/2014/8276132014(3-3)Online publication date: 13-Dec-2018
https://dl.acm.org/doi/10.1155/2014/827613
Briki AChavet CCoussy PMartin EBrunvard EStevens KCavallaro JZhang T(2012)A design approach dedicated to network-based and conflict-free parallel interleaversProceedings of the great lakes symposium on VLSI10.1145/2206781.2206819(153-158)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206819

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents