A design approach dedicated to network-based and conflict-free parallel interleavers

For high throughput applications, efficient parallel architectures require to avoid collision accesses, i.e. concurrent read/write accesses to the same memory bank have to be avoided. This consideration applies for example to the two main classes of turbo-like codes that are Low Density Parity Check (LDPC) and Turbo-Codes. These error correcting codes, that scramble data by using an interleaving law, are used in most of recent communication standards and storage systems like wireless access, digital video broadcasting or magnetic storage in hard disk drives. In order to optimize the architectural cost and to reduce the control complexity of such integrated circuits, designers usually use standard interconnection networks with low complexity topologies between processing elements and memory banks. However the design constraints, i.e. interleaving law, parallelism and interconnection network, often prevent mapping the data in the memory banks without any conflict. In this paper we propose a methodology which always finds a collision-free memory mapping for a given set of design constraints. The approach uses additional registers each time the design constraints forbid to use memory banks without conflict. Our approach is compared to state of the art methods and its interest is shown through the design of parallel interleavers for industrial applications: Multi Band-Orthogonal Frequency-Division Multiplexing Ultra-WideBand (MB-OFDM UWB) and non-binary LDPC decoders.