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research-article

Electronic system-level synthesis methodologies

Authors:

Andreas Gerstlauer,

Christian Haubelt,

Andy D. Pimentel,

Todor P. Stefanov,

Daniel D. Gajski,

Jürgen TeichAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 28, Issue 10

Pages 1517 - 1530

https://doi.org/10.1109/TCAD.2009.2026356

Published: 01 October 2009 Publication History

Abstract

With ever-increasing system complexities, all major semiconductor roadmaps have identified the need for moving to higher levels of abstraction in order to increase productivity in electronic system design. Most recently, many approaches and tools that claim to realize and support a design process at the so-called electronic system level (ESL) have emerged. However, faced with the vast complexity challenges, in most cases at best, only partial solutions are available. In this paper, we develop and propose a novel classification for ESL synthesis tools, and we will present six different academic approaches in this context. Based on these observations, we can identify such common principles and needs as they are leading toward and are ultimately required for a true ESL synthesis solution, covering the whole design process from specification to implementation for complete systems across hardware and software boundaries.

References

[1]

G. Martin, "Overview of the MPSoC design challenge," in Proc. DAC, San Francisco, CA, Jul. 2006, pp. 274-279.

Digital Library

[2]

D. Densmore, R. Passerone, and A. Sangiovanni-Vincentelli, "A platform-based taxonomy for ESL design," IEEE Des. Test Comput., vol. 23, no. 5, pp. 359-374, Sep./Oct. 2006.

Digital Library

[3]

E. A. Lee and A. Sangiovanni-Vincentelli, "A framework for comparing models of computation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 17, no. 12, pp. 1217-1229, Dec. 1998.

Digital Library

[4]

W. Wolf, A. A. Jerraya, and G. Martin, "Multiprocessor system-on-chip (MPSoC) technology," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 10, pp. 1701-1713, Oct. 2008.

Digital Library

[5]

J. Teich, "Embedded system synthesis and optimization," in Proc. Workshop SDA, Rathen, Germany, Mar. 2000, pp. 9-22.

[6]

D. D. Gajski and R. H. Kuhn, "New VLSI tools," Computer, vol. 16, no. 12, pp. 11-14, Dec. 1983.

Digital Library

[7]

C. Zhu, Z. P. Gu, R. P. Dick, and L. Shang, "Reliable multiprocessor system-on-chip synthesis," in Proc. CODES+ISSS, 2007, pp. 239-244.

Digital Library

[8]

S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, "Fabsyn: Floorplan-aware bus architecture synthesis," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 3, pp. 241-253, Mar. 2006.

Digital Library

[9]

{Online}. Available: http://www.forteds.com

[10]

NEC System Technologies, Ltd., CyberWorkBench. {Online}. Available: http://www.necst.co.jp/product/cwb

[11]

B. Kienhuis, E. Deprettere, P. van der Wolf, and K. Vissers, "A methodology to design programmable embedded systems," in Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation (SAMOS), vol. 2268. New York: Springer-Verlag, 2002, pp. 18-37.

Digital Library

[12]

M. Gries, "Methods for evaluating and covering the design space during early design development," Integr. VLSI J., vol. 38, no. 2, pp. 131-183, Dec. 2004.

Digital Library

[13]

D. D. Gajski, F. Vahid, S. Narayan, and J. Gong, Specification and Design of Embedded Systems. Englewood Cliffs, NJ: Prentice-Hall, 1994.

Digital Library

[14]

B. Kienhuis, E. Deprettere, K. Vissers, and P. van derWolf, "An approach for quantitative analysis of application-specific dataflow architectures," in Proc. IEEE Int. Conf. Appl.-Specific Syst., Architectures Processors, Zurich, Switzerland, Jul. 1997, pp. 338-349.

Digital Library

[15]

K. Huang, S. Han, K. Popovici, L. Brisolara, X. Guerin, L. Li, X. Yan, S. Chae, L. Carro, and A. A. Jerraya, "Simulink-based MPSoC design flow: Case study of Motion-JPEG and H.264," in Proc. DAC, 2007, pp. 39-42.

Digital Library

[16]

G. Stitt and F. Vahid, "Binary synthesis," ACM Trans. Des. Autom. Electron. Syst., vol. 12, no. 3, pp. 1-30, Aug. 2007.

Digital Library

[17]

K. Lahiri, A. Raghunathan, and S. Dey, "Design space exploration for optimizing on-chip communication architectures," IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 23, no. 6, pp. 952-961, Jun. 2004.

Digital Library

[18]

F. Dumitrascu, I. Bacivarov, L. Pieralisi, M. Bonaciu, and A. A. Jerraya, "Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application," in Proc. DATE Designers' Forum, 2006, pp. 166-171.

Digital Library

[19]

S. Pasricha and N. Dutt, "A framework for co-synthesis of memory and communication architectures for MPSoC," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 3, pp. 408-420, Mar. 2007.

Digital Library

[20]

M. Thompson, T. Stefanov, H. Nikolov, A. D. Pimentel, C. Erbas, S. Polstra, and E. F. Deprettere, "A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs," in Proc. CODES+ISSS, 2007, pp. 9-14.

Digital Library

[21]

H. Nikolov, M. Thompson, T. Stefanov, A. D. Pimentel, S. Polstra, R. Bose, C. Zissulescu, and E. F. Deprettere, "Daedalus: Toward composable multimedia MP-SoC design," in Proc. DAC, Jun. 2008, pp. 574-579.

Digital Library

[22]

G. Kahn, "The semantics of a simple language for parallel programming," in Proc. IFIP Congr., 1974, pp. 471-475.

[23]

S. Verdoolaege, H. Nikolov, and T. Stefanov, "PN: A tool for improved derivation of process networks," EURASIP J. Embed. Syst., vol. 2007, no. 1, p. 19, Jan. 2007. Article ID 75947.

Digital Library

[24]

A. D. Pimentel, C. Erbas, and S. Polstra, "A systematic approach to exploring embedded system architectures at multiple abstraction levels," IEEE Trans. Comput., vol. 55, no. 2, pp. 99-112, Feb. 2006.

Digital Library

[25]

H. Nikolov, T. Stefanov, and E. F. Deprettere, "Systematic and automated multi-processor system design, programming, and implementation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 3, pp. 542-555, Mar. 2008.

Digital Library

[26]

R. Dömer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, and D. D. Gajski, "System-on-chip environment: A SpecC-based framework for heterogeneous MPSoC design," EURASIP J. Embed. Syst., vol. 2008, no. 3, pp. 1-13, Jan. 2008.

Digital Library

[27]

D. D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, and S. Zhao, SpecC: Specification Language and Design Methodology. Norwell, MA: Kluwer, 2000.

[28]

A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, and Y. Nishihara, "Specify-explore-refine (SER): From specification to implementation," in Proc. DAC, Anaheim, CA, Jun. 2008, pp. 586-591.

Digital Library

[29]

J. Keinert, M. Streubühr, T. Schlichter, J. Falk, J. Gladigau, C. Haubelt, J. Teich, and M. Meredith, "SystemCoDesigner--An automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications," ACM Trans. Des. Autom. Electron. Syst., vol. 14, no. 1, pp. 1-23, Jan. 2009.

Digital Library

[30]

E. A. Lee and D. G. Messerschmitt, "Synchronous data flow," Proc. IEEE, vol. 75, no. 9, pp. 1235-1245, Sep. 1987.

[31]

G. Bilsen, M. Engels, R. Lauwereins, and J. Peperstraete, "Cyclo-static dataflow," IEEE Trans. Signal Process., vol. 44, no. 2, pp. 397-408, Feb. 1996.

Digital Library

[32]

T. Grötker, S. Liao, G. Martin, and S. Swan, System Design With SystemC. Norwell, MA: Kluwer, 2002.

Digital Library

[33]

K. Strehl, L. Thiele, M. Gries, D. Ziegenbein, R. Ernst, and J. Teich, "FunState--An internal design representation for codesign," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 4, pp. 524- 544, Aug. 2001.

Digital Library

[34]

C. Zebelein, J. Falk, C. Haubelt, and J. Teich, "Classification of general data flow actors into known models of computation," in Proc. MEMOCODE , Anaheim, CA, Jun. 2008, pp. 119-128.

[35]

J. Falk, J. Keinert, C. Haubelt, J. Teich, and S. Bhattacharyya, "A generalized static data flow clustering algorithm for MPSoC scheduling of multimedia applications," in Proc. EMSOFT, Atlanta, GA, Oct. 2008, pp. 189-198.

Digital Library

[36]

Embedded SystemTools Reference Manual--Embedded Development Kit EDK 8.1ia, XILINX, San Jose, CA, Oct. 2005. {Online}. Available: http://www.xilinx.com/ise/embedded/est_rm.pdf

[37]

F. Balarin, Y. Watanabe, H. Hsieh, L. Lavagno, C. Passerone, and A. Sangiovanni-Vincentelli, "Metropolis: An integrated electronic system design environment," Computer, vol. 36, no. 4, pp. 45-52, Apr. 2003.

Digital Library

[38]

A. Sangiovanni-Vincentelli, "Quo vadis SLD: Reasoning about the trends and challenges of system level design," Proc. IEEE, vol. 95, no. 3, pp. 467-506, Mar. 2007. {Online}. Available: http://chess.eecs. berkeley.edu/pubs/263.html

[39]

Gigascale Systems Research Center (GSRC), Core Design Technology for Complex Heterogeneous Systems. {Online}. Available: http://www. gigascale.org/theme/core/

[40]

T. Kangas, P. Kukkala, H. Orsila, E. Salminen, M. Hännikäinen, T. D. Hämäläinen, J. Riihimäki, and K. Kuusilinna, "UML-based multiprocessor SoC design framework," ACM Trans. Embed. Comput. Syst., vol. 5, no. 2, pp. 281-320, May 2006.

Digital Library

[41]

S. Ha, S. Kim, C. Lee, Y. Yi, S. Kwon, and Y.-P. Joo, "PeaCE: A hardware-software codesign environment of multimedia embedded systems," ACM Trans. Des. Autom. Electron. Syst., vol. 12, no. 3, pp. 1-25, Aug. 2007.

Digital Library

[42]

S. Kwon, Y. Kim,W.-C. Jeun, S. Ha, and Y. Paek, "A retargetable parallel programming framework forMPSoC," ACM Trans. Des. Autom. Electron. Syst., vol. 13, no. 3, pp. 1-18, Jul. 2008.

Digital Library

Cited By

Jordão RBecker MSander I(2024)IDeSyDe: Systematic Design Space Exploration via Design Space IdentificationACM Transactions on Design Automation of Electronic Systems10.1145/364764029:5(1-45)Online publication date: 10-Feb-2024
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Afshari FAbdi A(2024)Qsmix: Q-learning-based task scheduling approach for mixed-critical applications on heterogeneous multi-coresThe Journal of Supercomputing10.1007/s11227-024-06096-880:12(17895-17922)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1007/s11227-024-06096-8
Lovic GYohei I(2023)HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDLACM Transactions on Embedded Computing Systems10.1145/3581757Online publication date: 1-Feb-2023
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 28, Issue 10

October 2009

172 pages

ISSN:0278-0070

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Copyright © 2009.

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IEEE Press

Publication History

Published: 01 October 2009

Revised: 06 June 2009

Received: 24 February 2009

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Cited By

Jordão RBecker MSander I(2024)IDeSyDe: Systematic Design Space Exploration via Design Space IdentificationACM Transactions on Design Automation of Electronic Systems10.1145/364764029:5(1-45)Online publication date: 10-Feb-2024
https://dl.acm.org/doi/10.1145/3647640
Afshari FAbdi A(2024)Qsmix: Q-learning-based task scheduling approach for mixed-critical applications on heterogeneous multi-coresThe Journal of Supercomputing10.1007/s11227-024-06096-880:12(17895-17922)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1007/s11227-024-06096-8
Lovic GYohei I(2023)HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDLACM Transactions on Embedded Computing Systems10.1145/3581757Online publication date: 1-Feb-2023
https://dl.acm.org/doi/10.1145/3581757
Krishnakumar AOgras UMarculescu RKishinevsky MMudge T(2023)Domain-Specific Architectures: Research Problems and Promising ApproachesACM Transactions on Embedded Computing Systems10.1145/356394622:2(1-26)Online publication date: 24-Jan-2023
https://dl.acm.org/doi/10.1145/3563946
Zhang SYang LZhang YZhou XCui Z(2023)Data-Driven System-Level Design Framework for Responsible Cyber-Physical-Social SystemsComputer10.1109/MC.2023.324364556:4(80-91)Online publication date: 1-Apr-2023
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Trombetta VFelfernig AFuentes L(2022)BEEHIVEProceedings of the 26th ACM International Systems and Software Product Line Conference - Volume B10.1145/3503229.3547064(17-22)Online publication date: 12-Sep-2022
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Vu HNours SPillement SStemmer RGrüttner K(2021)A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoCProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431418(17-22)Online publication date: 18-Jan-2021
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Heinz CHofmann JKorinth JSommer LWeber LKoch A(2021)The TaPaSCo Open-Source ToolflowJournal of Signal Processing Systems10.1007/s11265-021-01640-893:5(545-563)Online publication date: 1-May-2021
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Le Nours SSingh D(2020)A Generic Executable Model for Fast Yet Accurate Contention Simulation in Multiprocessor SystemsIEEE Embedded Systems Letters10.1109/LES.2020.296680112:4(117-120)Online publication date: 1-Dec-2020
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