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pn: a tool for improved derivation of process networks

Published: 01 January 2007 Publication History

Abstract

Current emerging embedded System-on-Chip platforms are increasingly becoming multiprocessor architectures. System designers experience significant difficulties in programming these platforms. The applications are typically specified as sequential programs that do not reveal the available parallelism in an application, thereby hindering the effcient mapping of an application onto a parallel multiprocessor platform. In this paper, we present our compiler techniques for facilitating the migration from a sequential application specification to a parallel application specification using the process network model of computation. Our work is inspired by a previous research project called Compaan. With our techniques we address optimization issues such as the generation of process networks with simplified topology and communication without sacrificing the process networks' performance. Moreover, we describe a technique for compile-time memory requirement estimation which we consider as an important contribution of this paper. We demonstrate the usefulness of our techniques on several examples.

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Information & Contributors

Information

Published In

cover image EURASIP Journal on Embedded Systems
EURASIP Journal on Embedded Systems  Volume 2007, Issue 1
January 2007
474 pages
ISSN:1687-3955
EISSN:1687-3963
Issue’s Table of Contents

Publisher

Hindawi Limited

London, United Kingdom

Publication History

Published: 01 January 2007

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  • (2015)A Toolflow for Parallelization of Embedded Software in Multicore DSP PlatformsProceedings of the 18th International Workshop on Software and Compilers for Embedded Systems10.1145/2764967.2771936(76-79)Online publication date: 1-Jun-2015
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