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High-level synthesis of gracefully degradable ASICs

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Wah Chan,

A. OrailogluAuthors Info & Claims

EDTC '96: Proceedings of the 1996 European conference on Design and Test

Page 50

Published: 11 March 1996 Publication History

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Abstract

We propose a novel graceful degradation scheme, L/U reconfiguration, which can tolerate a single permanent fault in each hardware class of ASIC data paths. In the proposed scheme, dynamic hardware rebinding and operation rescheduling are performed by a systematic perturbation of the original configuration. A high-level synthesis procedure, which automatically generates such fault-tolerant systems, is also presented. Experiments show that our reconfigurable AISC designs, as compared to optimal nonfault-tolerant designs, achieve optimal pre-reconfiguration and near-optimal post-reconfiguration speed performance.

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Cited By

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Schölzel MDe Micheli GAl-Hashimi BMueller WMacii E(2010)HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data pathsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871101(723-728)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871101
Bolchini CPomante LSalice FSciuto D(2002)Reliability Properties Assessment at System LevelJournal of Electronic Testing: Theory and Applications10.1023/A:101504752498518:3(351-356)Online publication date: 1-Jun-2002
https://dl.acm.org/doi/10.1023/A%3A1015047524985
Bolchini CPomante LSalice FSciuto DHermida RAboulhamid E(2001)On-line fault detection in a hardware/software co-design environmentProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500013(51-56)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500013
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High-level synthesis of gracefully degradable ASICs
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Published In

EDTC '96: Proceedings of the 1996 European conference on Design and Test

March 1996

585 pages

ISBN:0818674237

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IEEE Computer Society

United States

Publication History

Published: 11 March 1996

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EDTC96

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SIGDA

EDTC96: European Design and Test Conference

March 11 - 14, 1996

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Cited By

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Schölzel MDe Micheli GAl-Hashimi BMueller WMacii E(2010)HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data pathsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871101(723-728)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871101
Bolchini CPomante LSalice FSciuto D(2002)Reliability Properties Assessment at System LevelJournal of Electronic Testing: Theory and Applications10.1023/A:101504752498518:3(351-356)Online publication date: 1-Jun-2002
https://dl.acm.org/doi/10.1023/A%3A1015047524985
Bolchini CPomante LSalice FSciuto DHermida RAboulhamid E(2001)On-line fault detection in a hardware/software co-design environmentProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500013(51-56)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500013
Hamilton SHertwig AOrailoğlu A(1999)Self recovering controller and datapath codesignProceedings of the conference on Design, automation and test in Europe10.1145/307418.307571(118-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307571
Hamilton SOrailoglu ADewilde PRammig FMusgrave G(1998)Concurrent error recovery with near-zero latency in synthesized ASICsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368307(604-611)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368307
Orailoğlu A(1998)On-Line Fault Resilience Through Gracefully Degradable ASICsJournal of Electronic Testing: Theory and Applications10.1023/A:100829822660012:1-2(145-151)Online publication date: 1-Feb-1998
https://dl.acm.org/doi/10.1023/A%3A1008298226600

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