Article

Free access

High-level synthesis of gracefully degradable ASICs

Authors:

Wah Chan,

A. OrailogluAuthors Info & Claims

EDTC '96: Proceedings of the 1996 European conference on Design and Test

Page 50

Published: 11 March 1996 Publication History

PDF eReader

Abstract

We propose a novel graceful degradation scheme, L/U reconfiguration, which can tolerate a single permanent fault in each hardware class of ASIC data paths. In the proposed scheme, dynamic hardware rebinding and operation rescheduling are performed by a systematic perturbation of the original configuration. A high-level synthesis procedure, which automatically generates such fault-tolerant systems, is also presented. Experiments show that our reconfigurable AISC designs, as compared to optimal nonfault-tolerant designs, achieve optimal pre-reconfiguration and near-optimal post-reconfiguration speed performance.

References

[1]

{1} W. Chan and A. Orailo¿lu. High-Level Synthesis of Gracefully Degradable ASICs. Technical Report CS95-447, Univ. of California, San Diego, Dept. of CSE, September 1995.

Google Scholar

[2]

{2} M. Chean and J. A. B. Fortes. A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays. IEEE Computer, 23(1):55-66, January 1990.

Digital Library

Google Scholar

[3]

{3} B. Iyer, R. Karri, and I. Koren. Phantom Redundancy: A High-Level Synthesis Approach for Manufacturability. In Proceedings of ICCAD, pages 658-661, November 1995.

Digital Library

Google Scholar

[4]

{4} K. H. Kernighan and S. Lin. An Efficient Heuristic Procedure for Partitioning Graph. Bell System Technical Journal, 49(2):291-307, February 1970.

Crossref

Google Scholar

[5]

{5} R. Naidu and S. Mahapatra. Fault Tolerance in N-MOS Random Access Memories with Dynamic Redundancy Methods. Microelectronics and Reliability, 28(2):193-200, 1988.

Crossref

Google Scholar

[6]

{6} R. Negrini, M. G. Sami, and R. Stefanelli. Fault Tolerance Through Reconfiguration in VLSi and WSI Arrays. MlT Press, 1989.

Google Scholar

[7]

{7} A. Orailo¿lu and R. Karri. Coactive Scheduling and Checkpoint Determination during High-Level Synthesis of Self-Recovering Microarchitectures. IEEE Transactions on VLSI Systems, 2(3):304-311, September 1994.

Digital Library

Google Scholar

[8]

{8} A. Orailo¿lu and R. Karri. Automatic Synthesis of Self-Recovering VLSI Systems. IEEE Transactions on Computers, February 1996.

Digital Library

Google Scholar

[9]

{9} P. G. Paulin and J. P. Knight. Algorithms for high-level synthesis. IEEE Design and Test of Computers, 6(6):18-31, December 1989.

Digital Library

Google Scholar

Cited By

View all

Schölzel MDe Micheli GAl-Hashimi BMueller WMacii E(2010)HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data pathsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871101(723-728)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871101
Bolchini CPomante LSalice FSciuto D(2002)Reliability Properties Assessment at System LevelJournal of Electronic Testing: Theory and Applications10.1023/A:101504752498518:3(351-356)Online publication date: 1-Jun-2002
https://dl.acm.org/doi/10.1023/A%3A1015047524985
Bolchini CPomante LSalice FSciuto DHermida RAboulhamid E(2001)On-line fault detection in a hardware/software co-design environmentProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500013(51-56)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500013
Show More Cited By

High-level synthesis of gracefully degradable ASICs
1. Computer systems organization

Recommendations

Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs
ICCD '96: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors

In this paper, we propose a novel fault-tolerance scheme, band reconfiguration, to handle multiple permanent faults in functional units of general ASIC designs. An associated high-level synthesis procedure that automatically generates such fault-...
On-Line Fault Resilience Through Gracefully Degradable ASICs
Special issue on On-line testing

We present two novel reconfiguration schemes, L/U reconfiguration and its generalization, band reconfiguration, to achieve graceful degradation for general microarchitecture datapaths. Upon detection of a datapath fault, hardware and algorithmic ...
From software to accelerators with LegUp high-level synthesis
CASES '13: Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

EDTC '96: Proceedings of the 1996 European conference on Design and Test

March 1996

585 pages

ISBN:0818674237

Publisher

IEEE Computer Society

United States

Publication History

Published: 11 March 1996

Check for updates

Author Tags

Qualifiers

Article

Conference

EDTC96

Sponsor:

SIGDA

EDTC96: European Design and Test Conference

March 11 - 14, 1996

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
122
Total Downloads

Downloads (Last 12 months)27
Downloads (Last 6 weeks)3

Reflects downloads up to 21 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Schölzel MDe Micheli GAl-Hashimi BMueller WMacii E(2010)HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data pathsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871101(723-728)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871101
Bolchini CPomante LSalice FSciuto D(2002)Reliability Properties Assessment at System LevelJournal of Electronic Testing: Theory and Applications10.1023/A:101504752498518:3(351-356)Online publication date: 1-Jun-2002
https://dl.acm.org/doi/10.1023/A%3A1015047524985
Bolchini CPomante LSalice FSciuto DHermida RAboulhamid E(2001)On-line fault detection in a hardware/software co-design environmentProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500013(51-56)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500013
Hamilton SHertwig AOrailoğlu A(1999)Self recovering controller and datapath codesignProceedings of the conference on Design, automation and test in Europe10.1145/307418.307571(118-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307571
Hamilton SOrailoglu ADewilde PRammig FMusgrave G(1998)Concurrent error recovery with near-zero latency in synthesized ASICsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368307(604-611)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368307
Orailoğlu A(1998)On-Line Fault Resilience Through Gracefully Degradable ASICsJournal of Electronic Testing: Theory and Applications10.1023/A:100829822660012:1-2(145-151)Online publication date: 1-Feb-1998
https://dl.acm.org/doi/10.1023/A%3A1008298226600

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs

On-Line Fault Resilience Through Gracefully Degradable ASICs

From software to accelerators with LegUp high-level synthesis