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Analog Device-Level Layout AutomationMay 2000
- Author:
- John M. Cohn
Abstract
No abstract available.
Cited By
- Lu Y, Chang Y and Chang Y WB-trees Proceedings of the 55th Annual Design Automation Conference, (1-6)
- Lu Y, Chang Y and Chang Y WB-Trees: A Meshed Tree Representation for FinFET Analog Layout Designs* 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), (1-6)
- Wu I, Ou H and Chang Y QB-trees Proceedings of the 53rd Annual Design Automation Conference, (1-6)
- Lin C, Lu C, Lin J and Chang S Routability-driven placement algorithm for analog integrated circuits Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design, (71-78)
- Tsao H, Chou P, Huang S, Chang Y, Lin M, Chen D and Liu D A corner stitching compliant B*-tree representation and its applications to analog placement Proceedings of the International Conference on Computer-Aided Design, (507-511)
- Wang S, Jia X, Yeh A and Zhang L (2011). Analog layout retargeting using geometric programming, ACM Transactions on Design Automation of Electronic Systems, 16:4, (1-11), Online publication date: 1-Oct-2011.
- Chen X, Hu J and Xu N Regularity-constrained floorplanning for multi-core processors Proceedings of the 2011 international symposium on Physical design, (99-106)
- He R and Zhang L Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts Proceedings of the 2010 Asia and South Pacific Design Automation Conference, (299-304)
- Lin C, Lin J, Huang C and Chang S Performance-driven analog placement considering boundary constraint Proceedings of the 47th Design Automation Conference, (292-297)
- Eick M, Strasser M, Graeb H and Schlichtmann U Automatic generation of hierarchical placement rules for analog integrated circuits Proceedings of the 19th international symposium on Physical design, (47-54)
- Graeb H, Balasa F, Castro-Lopez R, Chang Y, Fernandez F, Lin P and Strasser M Analog layout synthesis Proceedings of the Conference on Design, Automation and Test in Europe, (274-279)
- Xiao L and Young E Analog placement with common centroid and 1-D symmetry constraints Proceedings of the 2009 Asia and South Pacific Design Automation Conference, (353-360)
- Lin P, Zhang H, Wong M and Chang Y Thermal-driven analog placement considering device matching Proceedings of the 46th Annual Design Automation Conference, (593-598)
- Dong Q and Nakatake S Constraint-free analog placement with topological symmetry structure Proceedings of the 2008 Asia and South Pacific Design Automation Conference, (186-191)
- Zhang L, Shi C and Jiang Y Symmetry-aware placement with transitive closure graphs for analog layout design Proceedings of the 2008 Asia and South Pacific Design Automation Conference, (180-185)
- Lin P and Lin S Analog placement based on hierarchical module clustering Proceedings of the 45th annual Design Automation Conference, (50-55)
- Ma Q, Young E and Pun K Analog placement with common centroid constraints Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, (579-585)
- Rutenbar R Design automation for analog Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, (458-460)
- Tam Y, Young E and Chu C Analog placement with symmetry and other placement constraints Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, (349-354)
- Kouda S, Kodama C and Fujiyoshi K Improved method of cell placement with symmetry constraints for analog IC layout design Proceedings of the 2006 international symposium on Physical design, (192-199)
- Agarwal A and Vemuri R Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners Proceedings of the 2005 International Conference on Computer Design, (444-452)
- Zhang L, Raut R, Jiang Y, Kleine U and Kim Y (2005). Macro-cell placement for analog physical designs using a hybrid genetic algorithm with simulated annealing, Integrated Computer-Aided Engineering, 12:4, (379-396), Online publication date: 1-Oct-2005.
- Gielen G, McConaghy T and Eeckelaert T Performance space modeling for hierarchical synthesis of analog integrated circuits Proceedings of the 42nd annual Design Automation Conference, (881-886)
- Schreiner L, Olbrich M, Barke E and Meyer zu Bexten V Routing of analog busses with parasitic symmetry Proceedings of the 2005 international symposium on Physical design, (14-19)
- Nojima T, Zhu X, Takashima Y, Nakatake S and Kajitani Y Multi-level placement with circuit schema based clustering in analog IC layouts Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (406-411)
- Nojima T, Takashima Y, Nakatake S and Kajitani Y A device-level placement with multi-directional convex clustering Proceedings of the 14th ACM Great Lakes symposium on VLSI, (196-201)
- Balasa F, Maruvada S and Krishnamoorthy K Using red-black interval trees in device-level analog placement with symmetry constraints Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (777-782)
- Kubo Y, Nakatake S, Kajitani Y and Kawakita M Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts Proceedings of the 2002 Asia and South Pacific Design Automation Conference
- Balasa F, Maruvada S and Krishnamoorthy K Efficient solution space exploration based on segment trees in analog placement with symmetry constraints Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (497-502)
- Gopalakrishnan P and Rutenbar R Direct transistor-level layout for digital blocks Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (577-584)
- Balasa F Device-level placement for analog layout Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (281-286)
- Gielen G and Rutenbar R Synthesis of analog and mixed-signal integrated electronic circuits Formal engineering design synthesis, (391-427)
- Balasa F Modeling non-slicing floorplans with binary trees Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, (13-16)
- Rutenbar R and Cohn J Layout tools for analog ICs and mixed-signal SoCs Proceedings of the 2000 international symposium on Physical design, (76-83)
- Balasa F and Lampaert K Module placement for analog layout using the sequence-pair representation Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (274-279)
- Riepe M and Sakallah K Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis Proceedings of the 1999 international symposium on Physical design, (74-81)
- Aktuna M, Rutenbar R and Carley L Device-level early floorplanning algorithms for RF circuits Proceedings of the 1998 international symposium on Physical design, (57-64)
- Arsintescu B and Spânoche S Global stacking for analog circuits Proceedings of the conference on European design automation, (392-397)
- Carley L, Gielen G, Rutenbar R and Sansen W Synthesis tools for mixed-signal ICs Proceedings of the 33rd annual Design Automation Conference, (298-303)
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