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research-article

Performance-driven analog placement considering boundary constraint

Authors:

Soon-Jyh ChangAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 292 - 297

https://doi.org/10.1145/1837274.1837348

Published: 13 June 2010 Publication History

Abstract

To reduce parasitic mismatches in analog design, we usually care about the property of symmetric placement for symmetry groups, which would form several symmetry islands in a chip. However, routing is greatly affected by placement results. If modules with input or output ports are placed arbitrarily in a symmetry island, the routing wires, which connect these modules with other modules outside the island, may induce unwanted parasitics coupling to signals, and thus circuit performance is deteriorated. This phenomenon can not be identified by a cost function, which only considers placement area and total wire length. Therefore, we would like to introduce the necessity of considering boundary constraint for the modules with input or output ports in symmetry islands. Based on ASF-B* tree [3], we explore the feasible conditions for 1D and 2D symmetry islands to meet this constraint. Further, a procedure is presented to maintain the feasibility for each ASF-B* tree after perturbation. Experimental results show that our approach guarantees the boundary property for the modules with input or output ports in symmetry islands.

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Cited By

Xu PLi JHo TYu BZhu K(2024)Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473859
Zhu KChen HLiu MPan D(2023)Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal FlowIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323036742:8(2689-2702)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3230367
Lin YLi YFang DMadhusudan MSapatnekar SHarjani RHu J(2022)Are Analytical Techniques Worthwhile for Analog IC Placement?2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774498(154-159)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774498
Show More Cited By

Index Terms

Performance-driven analog placement considering boundary constraint
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

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Published: 13 June 2010

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National Science Council Taiwan

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DAC '10

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EDAC
SIGDA

DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Xu PLi JHo TYu BZhu K(2024)Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473859
Zhu KChen HLiu MPan D(2023)Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal FlowIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323036742:8(2689-2702)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3230367
Lin YLi YFang DMadhusudan MSapatnekar SHarjani RHu J(2022)Are Analytical Techniques Worthwhile for Analog IC Placement?2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774498(154-159)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774498
Budak APan DChen HZhu KLiu MAlawieh MZhang SShi WTang X(2022)CAD for Analog/Mixed‐Signal Integrated CircuitsAdvances in Semiconductor Technologies10.1002/9781119869610.ch3(43-60)Online publication date: 30-Sep-2022
https://doi.org/10.1002/9781119869610.ch3
Zhu KChen HLiu MTang XSun NPan DXie Y(2020)Effective analog/mixed-signal circuit placement considering system signal flowProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415625(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415625
Li YLin YMadhusudan MSharma AXu WSapatnekar SHarjani RHu J(2020)Exploring a Machine Learning Approach to Performance Driven Analog IC Placement2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI49217.2020.00015(24-29)Online publication date: Jul-2020
https://doi.org/10.1109/ISVLSI49217.2020.00015
Lu YChang YChang Y(2018)WB-treesProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196137(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196137
Xu BLi SXu XSun NPan DOzdal MChu C(2017)Hierarchical and Analytical Placement Techniques for High-Performance Analog CircuitsProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036678(55-62)Online publication date: 19-Mar-2017
https://dl.acm.org/doi/10.1145/3036669.3036678
Wu IOu HChang Y(2016)QB-treesProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898074(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898074
Lin MChang YHung C(2016)Recent research development and new challenges in analog layout synthesis2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428080(617-622)Online publication date: Jan-2016
https://doi.org/10.1109/ASPDAC.2016.7428080
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