Regularity-constrained floorplanning for multi-core processors

Multi-core technology becomes a new engine that drives performance growth for both microprocessors and embedded computing. This trend asks chip floorplanners to consider regularity constraint since identical processing/memory cores are preferred to form an array in layout. As chip core count keeps growing, manual floorplanning will be inefficient on the solution space exploration while conventional floorplanning algorithms do not address the regularity constraint. In this work, we investigate how to enforce regularity constraint in a simulated-annealing based floorplanner. We propose a simple and effective technique for encoding the regularity constraint in sequence-pairs. To the best of our knowledge, this is the first work on regularity-constrained floorplanning in the context of multi-core processor designs. Experimental comparison with a semi-automatic method shows that our approach yields an average of 22% less wirelength and mostly smaller area.