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research-article

Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies

Authors:

Jörg HenkelAuthors Info & Claims

CASES '13: Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

Article No.: 11, Pages 1 - 10

Published: 29 September 2013 Publication History

Abstract

Two key parameters that determine the performance of a DRAM cache based multi-core system are DRAM cache hit latency (HL) and DRAM cache miss rate (MR), as they strongly influence the average DRAM cache access latency. Recently proposed DRAM set mapping policies are either optimized for HL or for MR. None of these policies provides a good HL and MR at the same time. This paper presents a novel DRAM set mapping policy that simultaneously targets both parameters with the goal of achieving the best of both to reduce the overall DRAM cache access latency. For a 16-core system, our proposed set mapping policy reduces the average DRAM cache access latency (depends upon HL and MR) compared to state-of-the-art DRAM set mapping policies that are optimized for either HL or MR by 29.3% and 12.1%, respectively.

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Cited By

Modi GBagchi AJindal NMandal APanda P(2023)CABARRE: Request Response Arbitration for Shared Cache ManagementACM Transactions on Embedded Computing Systems10.1145/360809622:5s(1-24)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3608096
Khan AHameed FCastrillon JChillet D(2018)NVMain Extension for Multi-Level Cache SystemsProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180672(1-6)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.1145/3180665.3180672
Hameed FCastrillon J(2017)Rethinking on-chip DRAM cache for simultaneous performance and energy optimizationProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130465(362-367)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130465
Show More Cited By

Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information & Contributors

Information

Published In

cover image ACM Conferences

CASES '13: Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

September 2013

247 pages

ISBN:9781479914005

Program Chairs:
Rodric Rabbah
IBM Research
,
Anand Raghunathan
Purdue University

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Publisher

IEEE Press

Publication History

Published: 29 September 2013

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Research-article

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ESWEEK'13

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ESWEEK'13: Ninth Embedded System Week

September 29 - October 4, 2013

Quebec, Montreal, Canada

Acceptance Rates

CASES '13 Paper Acceptance Rate 21 of 68 submissions, 31%;

Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

Modi GBagchi AJindal NMandal APanda P(2023)CABARRE: Request Response Arbitration for Shared Cache ManagementACM Transactions on Embedded Computing Systems10.1145/360809622:5s(1-24)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3608096
Khan AHameed FCastrillon JChillet D(2018)NVMain Extension for Multi-Level Cache SystemsProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180672(1-6)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.1145/3180665.3180672
Hameed FCastrillon J(2017)Rethinking on-chip DRAM cache for simultaneous performance and energy optimizationProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130465(362-367)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130465
Hameed FMenard CCastrillon JJacob B(2017)Efficient STT-RAM last-level-cache architecture to replace DRAM cacheProceedings of the International Symposium on Memory Systems10.1145/3132402.3132414(141-151)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132414
Chaudhuri MAgrawal MGaur JSubramoney S(2017)Micro-Sector CacheACM Transactions on Architecture and Code Optimization10.1145/304668014:1(1-29)Online publication date: 21-Mar-2017
https://dl.acm.org/doi/10.1145/3046680
Tschirhart PStevens JChishti ZJacob BJacob B(2016)The Case for Associative DRAM CachesProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989120(211-219)Online publication date: 3-Oct-2016
https://dl.acm.org/doi/10.1145/2989081.2989120
Ryoo JMeswani MPanda RJohn LZaks AMendelson BRauchwerger LHwu W(2016)POSTERProceedings of the 2016 International Conference on Parallel Architectures and Compilation10.1145/2967938.2974060(435-437)Online publication date: 11-Sep-2016
https://dl.acm.org/doi/10.1145/2967938.2974060
Yin SLi JLiu LWei SGuo YNebel WAtienza D(2015)Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cacheProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755794(187-192)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755794
Uppal AMeswani M(2015)Towards Workload-Aware Page Cache Replacement Policies for Hybrid MemoriesProceedings of the 2015 International Symposium on Memory Systems10.1145/2818950.2818978(206-219)Online publication date: 5-Oct-2015
https://dl.acm.org/doi/10.1145/2818950.2818978
Hameed FBauer LHenkel J(2014)Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache ArchitectureProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593197(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593197

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