[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/369691.369763acmconferencesArticle/Chapter ViewAbstractPublication PagesispdConference Proceedingsconference-collections
Article

Interconnect characteristics of 2.5-D system integration scheme

Published: 01 April 2001 Publication History

Abstract

Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing chip size. To address this problem instead of placing all systems components in one layer (i.e. in 2-D space) one can use a stack of single layer monolithic ICs (called here a 2.5-D integrated IC). To assess the potential benefits of such a 2.5-D integration schema this paper compares wire length distributions, obtained for 2-D and 2.5-D implementations of benchmark circuits. In the assessment two newly developed floorplanning and placement tools were used. Significant reductions in both total wirelength and worst-case wirelength was observed for the systems implemented as 2.5-D ICs.

References

[1]
M. Bohr, "Interconnect Scaling - the Real Limiter to High Performance ULSI," Proceedings of IEDM 1995, pp. 241- 244.
[2]
W. P. Maly, D. B. I. Feltham, A. E. Gattiker, M. D. Hobaugh, K. Backus and M. E. Thomas, "Multi-Chip Module Smart Substrate Systems ", IEEE Design & Test of Computers, Summer 1994, pp. 64-73.
[3]
K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashmoto, K. T. Park, H. Kurino and M. Koyanagi, "Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology," Proceedings of IEDM- 2000, 165-168.
[4]
K. Kozminski, "Benchmarks for Layout Synthesis," Proceedings of DAC, 1991, 265-270.
[5]
S. Nakatake, H. Murata, K. Fujiyoshi, and Y. Kajitani, "Module placement on BSG-structure and IC layout applications," Proceedings of ACM/IEEE ICCAD, Nov. 1996, pp. 484-491.
[6]
A. E. Caldwell, A. B. Kahng and I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?" Proceedings of Design Automation Conf. 2000, 477-482.
[7]
A. E. Dunlop and B. W. Kernighan, "A Procedure for Placement of Standard Cell VLSI Circuits," IEEE Transactions on Computer-aided Design of Integrated Circuits and System, No.4, Vol.1, 1985, 92-98.
[8]
C. -L. E. Cheng, "RISA: Accurate and Efficient Placement Routability Modeling," Proceedings of ICCAD 1994, 690- 694.

Cited By

View all
  • (2024)Multi-Objective Optimization in 3D FloorplanningElectronics10.3390/electronics1309169613:9(1696)Online publication date: 27-Apr-2024
  • (2024)Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334729343:6(1624-1637)Online publication date: Jun-2024
  • (2024)Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00068(876-889)Online publication date: 29-Jun-2024
  • Show More Cited By

Index Terms

  1. Interconnect characteristics of 2.5-D system integration scheme

        Recommendations

        Comments

        Please enable JavaScript to view thecomments powered by Disqus.

        Information & Contributors

        Information

        Published In

        cover image ACM Conferences
        ISPD '01: Proceedings of the 2001 international symposium on Physical design
        April 2001
        245 pages
        ISBN:1581133472
        DOI:10.1145/369691
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Sponsors

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        Published: 01 April 2001

        Permissions

        Request permissions for this article.

        Check for updates

        Author Tags

        1. 2.5-D system integration
        2. VLSI
        3. bounded sliceline grid
        4. floorplanning
        5. partition
        6. placement
        7. wirelength

        Qualifiers

        • Article

        Conference

        ISPD01
        Sponsor:
        ISPD01: International Symposium on Physical Design
        April 1 - 4, 2001
        California, Sonoma, USA

        Acceptance Rates

        Overall Acceptance Rate 62 of 172 submissions, 36%

        Upcoming Conference

        ISPD '25
        International Symposium on Physical Design
        March 16 - 19, 2025
        Austin , TX , USA

        Contributors

        Other Metrics

        Bibliometrics & Citations

        Bibliometrics

        Article Metrics

        • Downloads (Last 12 months)36
        • Downloads (Last 6 weeks)5
        Reflects downloads up to 13 Dec 2024

        Other Metrics

        Citations

        Cited By

        View all
        • (2024)Multi-Objective Optimization in 3D FloorplanningElectronics10.3390/electronics1309169613:9(1696)Online publication date: 27-Apr-2024
        • (2024)Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334729343:6(1624-1637)Online publication date: Jun-2024
        • (2024)Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00068(876-889)Online publication date: 29-Jun-2024
        • (2023)Survey of Reliability Research on 3D Packaged MemoryElectronics10.3390/electronics1212270912:12(2709)Online publication date: 17-Jun-2023
        • (2020)Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study2020 IEEE 33rd International System-on-Chip Conference (SOCC)10.1109/SOCC49529.2020.9524798(277-282)Online publication date: 8-Sep-2020
        • (2019)Decreasing latency considering power consumption issue in silicon interposer-based network-on-chipThe Journal of Supercomputing10.1007/s11227-019-02964-wOnline publication date: 21-Aug-2019
        • (2019)An expandable topology with low wiring congestion for silicon interposer‐based network‐on‐chip systemsTransactions on Emerging Telecommunications Technologies10.1002/ett.374730:12Online publication date: 10-Dec-2019
        • (2017)InvisiMemACM SIGARCH Computer Architecture News10.1145/3140659.308023245:2(94-106)Online publication date: 24-Jun-2017
        • (2017)InvisiMemProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080232(94-106)Online publication date: 24-Jun-2017
        • (2017)Silica-Embedded Silicon Nanophotonic On-Chip NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261151636:6(978-991)Online publication date: 1-Jun-2017
        • Show More Cited By

        View Options

        Login options

        View options

        PDF

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader

        Media

        Figures

        Other

        Tables

        Share

        Share

        Share this Publication link

        Share on social media