article

IBM POWER7 systems

Authors:

R. X. Arroyo,

R. J. Harrington,

S. P. Hartman,

T. NguyenAuthors Info & Claims

IBM Journal of Research and Development, Volume 55, Issue 3

Pages 220 - 232

https://doi.org/10.1147/JRD.2011.2131610

Published: 01 May 2011 Publication History

Abstract

This paper describes the system architectures and designs of the IBM POWER7^® servers. From the smallest single-processor socket blade to the largest 32-processor-socket 256-core enterprise rack server, each system is designed to fully exploit the performance and the scalability of the POWER7 processor. This paper describes the enhancements made to the memory and input/output subsystems to achieve balanced and scalable designs, the changes made to the power and cooling circuitry to manage energy consumption and power dissipation, and the enhancements made to reliability, availability, and serviceability. These enhancements enable the POWER7 processor-based servers to achieve significant increases in the performance density and the performance per watt, as compared with the predecessor POWER6^® processor-based servers.

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Hameed FBauer LHenkel J(2016)Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency ReductionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.248848835:4(651-664)Online publication date: 17-Mar-2016
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cover image IBM Journal of Research and Development

IBM Journal of Research and Development Volume 55, Issue 3

May 2011

144 pages

ISSN:0018-8646

Issue’s Table of Contents

Publisher

IBM Corp.

United States

Publication History

Published: 01 May 2011

Accepted: 21 February 2011

Received: 29 November 2010

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Hameed FMenard CCastrillon JJacob B(2017)Efficient STT-RAM last-level-cache architecture to replace DRAM cacheProceedings of the International Symposium on Memory Systems10.1145/3132402.3132414(141-151)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132414
Chaudhuri MAgrawal MGaur JSubramoney S(2017)Micro-Sector CacheACM Transactions on Architecture and Code Optimization10.1145/304668014:1(1-29)Online publication date: 21-Mar-2017
https://dl.acm.org/doi/10.1145/3046680
Hameed FBauer LHenkel J(2016)Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency ReductionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.248848835:4(651-664)Online publication date: 17-Mar-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2488488
Becker WHarrer HHuber ABrodsky WKrabbenhoft RCracraft MKaller DEdlund GStrach T(2015)Electronic packaging of the IBM z13 processor drawerIBM Journal of Research and Development10.1147/JRD.2015.244503159:4-5(13:1-13:12)Online publication date: 1-Jul-2015
https://dl.acm.org/doi/10.1147/JRD.2015.2445031
Cahill JNguyen TVega MBaska DSzerdi DPross HArroyo RNguyen HMueller MHenderson DMoreira J(2015)IBM power systems built with the POWER8 architecture and processorsIBM Journal of Research and Development10.1147/JRD.2014.237613259:1(4:1-4:10)Online publication date: 1-Jan-2015
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Starke WStuecheli JDaly DDodson JAuernhammer FSagmeister PGuthrie GMarino CSiegel MBlaner B(2015)The cache and memory subsystems of the IBM POWER8 processorIBM Journal of Research and Development10.1147/JRD.2014.237613159:1(3:1-3:13)Online publication date: 1-Jan-2015
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Hameed FBauer LHenkel J(2014)Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache ArchitectureProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593197(1-6)Online publication date: 1-Jun-2014
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Que XChecconi FPetrini F(2014)Performance Analysis of Graph Algorithms on P7IHProceedings of the 29th International Conference on Supercomputing - Volume 848810.1007/978-3-319-07518-1_7(109-123)Online publication date: 22-Jun-2014
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Hameed FBauer LHenkel JRabbah RRaghunathan A(2013)Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policiesProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555740(1-10)Online publication date: 29-Sep-2013
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Hameed FBauer LHenkel JMarculescu RPanda P(2013)Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cacheProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555693(1-8)Online publication date: 29-Sep-2013
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