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- abstractAugust 2024
Machine Learning in Finance
- Leman Akoglu,
- Nitesh Chawla,
- Josep Domingo-Ferrer,
- Eren Kurshan,
- Senthil Kumar,
- Vidyut Naware,
- Jose A. Rodriguez-Serrano,
- Isha Chaturvedi,
- Saurabh Nagrecha,
- Mahashweta Das,
- Tanveer Faruquie
KDD '24: Proceedings of the 30th ACM SIGKDD Conference on Knowledge Discovery and Data MiningPage 6703https://doi.org/10.1145/3637528.3671488This workshop aims to explore the intersection of Generative AI with the rich tapestry of financial data types, seeking to uncover new methodologies and techniques that can enhance predictive analytics, fraud detection, and customer insights across the ...
- research-articleMay 2022
On the current and emerging challenges of developing fair and ethical AI solutions in financial services
ICAIF '21: Proceedings of the Second ACM International Conference on AI in FinanceArticle No.: 43, Pages 1–8https://doi.org/10.1145/3490354.3494408AI has found a wide range of application areas in the financial services industry. As the number and the criticality of the applications continue to increase, fair and ethical AI has emerged as an industry-wide objective. In recent years, numerous ...
- research-articleOctober 2021
Towards self-regulating AI: challenges and opportunities of AI model governance in financial services
ICAIF '20: Proceedings of the First ACM International Conference on AI in FinanceArticle No.: 49, Pages 1–8https://doi.org/10.1145/3383455.3422564AI systems have found a wide range of application areas in financial services. Their involvement in broader and increasingly critical decisions has escalated the need for compliance and effective model governance. Current governance practices have ...
- research-articleOctober 2021
Deep Q-network-based adaptive alert threshold selection policy for payment fraud systems in retail banking
ICAIF '20: Proceedings of the First ACM International Conference on AI in FinanceArticle No.: 24, Pages 1–7https://doi.org/10.1145/3383455.3422563Machine learning models have widely been used in fraud detection systems. Most of the research and development efforts have been concentrated on improving the performance of the fraud scoring models. Yet, the downstream fraud alert systems still have ...
- research-articleSeptember 2017
Thermomechanical Stress-Aware Management for 3-D IC Designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 25, Issue 9Pages 2678–2682https://doi.org/10.1109/TVLSI.2017.2707119Thermal characteristics have been considered as one of the most challenging problems in 3-D integrated circuits (3-D ICs). Due to the thermal expansion coefficient mismatch between through-silicon vias (TSVs) and the silicon substrate, and the presence of ...
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- research-articleMay 2017
Security Threats and Countermeasures in Three-Dimensional Integrated Circuits
GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017Pages 321–326https://doi.org/10.1145/3060403.3060500Existing works on Three-dimensional (3D) hardware security focus on leveraging the unique 3D characteristics to address the supply chain attacks that exist in 2D design. However, 3D ICs introduce specific and unexplored challenges as well as new ...
- opinionJanuary 2017
Editorial
- Krishnendu Chakrabarty,
- Massimo Alioto,
- Bevan M. Baas,
- Chirn Chye Boon,
- Meng-Fan Chang,
- Naehyuck Chang,
- Yao-Wen Chang,
- Chip-Hong Chang,
- Shih-Chieh Chang,
- Poki Chen,
- Masud Chowdhury,
- Pasquale Corsonello,
- Ibrahim M. Abe Elfadel,
- Said Hamdioui,
- Masanori Hashimoto,
- Tsung-Yi Ho,
- Houman Homayoun,
- Yuh-Shyan Hwang,
- Rajiv V. Joshi,
- Tanay Karnik,
- Mehran Mozaffari Kermani,
- Chulwoo Kim,
- Tae-Hyoung Kim,
- Jaydeep P. Kulkarni,
- Eren Kursun,
- Erik Larsson,
- Hai Helen Li,
- Huawei Li,
- Patrick Mercier,
- Prabhat Mishra,
- Makoto Nagata,
- Arun S. Natarajan,
- Koji Nii,
- Partha Pratim Pande,
- Ioannis Savidis,
- Mingoo Seok,
- Sheldon Tan,
- M. Tehranipoor,
- Aida Todri-Sanial,
- Miroslav N. Velev,
- Miroslav N. Velev,
- Jiang Xu,
- Wei Zhang,
- Zhengya Zhang,
- Stacey Weber Jackson
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 25, Issue 1Pages 1–20https://doi.org/10.1109/TVLSI.2016.2638578As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great ...
- research-articleMay 2016
Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges
GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSIPages 347–352https://doi.org/10.1145/2902961.29035123D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans,...
- research-articleOctober 2013
Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory
ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 9, Issue 3Article No.: 22, Pages 1–22https://doi.org/10.1145/2491679Improving the vulnerability to soft errors is one of the important design goals for future architecture design of Chip-MultiProcessors (CMPs). In this study, we explore the soft error characteristics of CMPs with 3D stacked NonVolatile Memory (NVM), in ...
- research-articleSeptember 2013
Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 32, Issue 9Pages 1335–1346https://doi.org/10.1109/TCAD.2013.22611203-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the ...
- research-articleMarch 2013
Thermomechanical stress-aware management for 3D IC designs
The thermomechanical stress has been considered as one of the most challenging problems in three-dimensional integration circuits (3D ICs), due to the thermal expansion coefficient mismatch between the through-silicon vias (TSVs) and silicon substrate, ...
- research-articleAugust 2012
Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 8, Issue 3Article No.: 21, Pages 1–17https://doi.org/10.1145/2287696.2287704Three-dimensional integration provides a new way of performance growth for microprocessor architectures. While a recent studies report promising performance improvement numbers, majority of the processor stacking options are thermally-limited. Elevated ...
- research-articleJuly 2012
Fast poisson solvers for thermal analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17, Issue 3Article No.: 32, Pages 1–23https://doi.org/10.1145/2209291.2209305Accurate and efficient thermal analysis for a VLSI chip is crucial, both for sign-off reliability verification and for design-time circuit optimization. To determine an accurate temperature profile, it is important to simulate a die together with its ...
- research-articleJune 2012
An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring
DAC '12: Proceedings of the 49th Annual Design Automation ConferencePages 642–647https://doi.org/10.1145/2228360.2228476Full-chip thermal monitoring is an important and challenging issue in today's microprocessor design. In this paper, we propose a new information-theoretic framework to quantitatively model the uncertainty of on-chip temperature variation by differential ...
- ArticleOctober 2011
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory
ICCD '11: Proceedings of the 2011 IEEE 29th International Conference on Computer DesignPages 366–372https://doi.org/10.1109/ICCD.2011.6081425Spin-transfer Torque Random Access Memory (STT-RAM) emerges for on-chip memory in microprocessor architectures. Thanks to the magnetic field based storage STT-RAM cells have immunity to radiation induced soft errors that affect electrical charge based ...
- research-articleAugust 2011
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and designPages 397–402The three-dimensional integrated circuits (3D ICs) offer performance advantages thanks to the increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal ...
- research-articleJune 2011
Design, CAD and technology challenges for future processors: 3D perspectives
DAC '11: Proceedings of the 48th Design Automation ConferencePage 212https://doi.org/10.1145/2024724.2024772Technology scaling has provided the semiconductor industry a recipe to successfully meet the application demands for performance for over three decades. This computational capacity was further fueled by the success of circuit and architecture-level ...
- research-articleMay 2011
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities
- Victor Jimenez,
- Francisco Cazorla,
- Roberto Gioiosa,
- Eren Kursun,
- Canturk Isci,
- Alper Buyuktosunoglu,
- Pradip Bose,
- Mateo Valero
Proposals have focused on reducing energy requirements for large-scale computing facilities (LSCFs), but little research has addressed the need for energy-usage-based accounting. Energy-aware accounting and billing benefits LSCF owners and users. This ...
- research-articleFebruary 2011
Exploring the effects of on-chip thermal variation on high-performance multicore architectures
ACM Transactions on Architecture and Code Optimization (TACO), Volume 8, Issue 1Article No.: 2, Pages 1–22https://doi.org/10.1145/1952998.1953000Inherent temperature variation among cores in a multicore architecture can be caused by a number of factors including process variation, cooling and packaging imperfections, and even placement of the chip in the module. Current dynamic thermal management ...
- research-articleSeptember 2010
Power and thermal characterization of POWER6 system
- Victor Jiménez,
- Francisco J. Cazorla,
- Roberto Gioiosa,
- Mateo Valero,
- Carlos Boneti,
- Eren Kursun,
- Chen-Yong Cher,
- Canturk Isci,
- Alper Buyuktosunoglu,
- Pradip Bose
PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniquesPages 7–18https://doi.org/10.1145/1854273.1854281Controlling power consumption and temperature is of major concern for modern computing systems. In this work we characterize thermal behavior and power consumption of an IBM POWER6-based system. We perform the characterization at several levels: ...