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ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
2011 Proceeding
Publisher:
  • IEEE Press
Conference:
ISLPED'11: International Symposium on Low Power Electronics and Design Fukuoka Japan August 1 - 3, 2011
ISBN:
978-1-61284-660-6
Published:
01 August 2011
Sponsors:
SIGDA, IEEE CAS

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Abstract

Welcome to the 17th IEEE/ACM International Symposium on Low-power Electronics and Design. The 2011 edition of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'11) welcomes you to Fukuoka, capital city of Fukuoka Prefecture in Kyushu, Japan. This is the first time ISLPED has been held in Japan. Since the earthquake and tsunami on March 11, Japan has been under difficult circumstances in terms of power. Accordingly, this year, Japan is the ideal place to discuss low-power electronics and design.

Fukuoka is home to a vibrant semiconductor cluster comprised of research and development divisions of major semiconductor manufacturers, such as Sony, NEC Electronics, Toshiba, Hitachi and Panasonic, as well as start-up companies with groundbreaking technologies. In turn, this cluster has led to active joint research and development between universities and companies. Moreover, a growing number of spin-off ventures and start-up ventures are being launched from universities. Fukuoka is also promoting the Silicon Sea Belt Fukuoka Project, a partnership between about 200 semiconductor firms and universities, research institutions, and government in Japan that aims to make Fukuoka a design and development center for high-value-added LSI chips in the "Asian Silicon Sea Belt Zone."

This year's symposium features strong and diverse technical sessions on the hottest topics in low-power electronics and design. We would like to thank the Program Committee members for their extensive efforts and welcome five keynote talks from leaders in industry and academia.

This year ISLPED has four distinguished keynote speakers over three days. On the first day, Dr. Toshihiro Hattori, VP of SoC Business Division, Renesas Mobile, will introduce low-power and high-performance technologies for mobile system-on-chips---whose demand is rapidly increasing thanks to smart phones and tablet computers. On the second day, Dr. Kee Sup Kim of Samsung Electronics will talk about holistic low-power solutions for a new world and explore where else low-power technology developed for the semiconductor industry can be applied. On the third day, Prof. Sachin Sapatnekar of the Univ. of Minnesota will introduce the "hows and whys" of thermal management for future systems providing an overview of challenges and opportunities. After that, Dr. Yasunori Miyahara of Panasonic will talk about trends in next-generation wireless technologies for ultra-low energy. These keynote speeches will visualize present status and future perspective of low-power system design.

The conference also features two special sessions and an embedded tutorial. The first special session, held on the first day of the conference, features Prof. Takayasu Sakurai from The University of Tokyo, Prof. Toshiro Hiramoto from The University of Tokyo, and Prof. Mitsumasa Koyanagi from Tohoku University, who will ndiscuss technological and methodological issues involved in ultra-low-voltage operation of digital circuits. The second special session, held on the last day of the conference, features Prof. Satoshi Matsuoka from the Tokyo Institute of Technology, Prof. Ken Takeuchi from The University of Tokyo, and Dr. Mitsuo Yokokawa from RIKEN, and will focus on how to enable green and high-performance computing. The embedded tutorial by Dr. Manuj Sabharwal from Intel Corporation will focus on software power optimization, in particular, on best practices for writing energy-efficient applications.

We have prepared an exciting technical program for ISLPED 2011. Out of 201 paper submissions, 66 were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 22.4% for regular and short papers (45 papers), or 32.8% including the 21 posters. Topics span low-power and emerging technologies, circuits, and memories; low-voltage analog and RF design; power-aware design and tools; power-efficient architecture techniques; and system and application-level power optimization.

The program is organized into 11 technical sessions featuring long- (30 min) and short- (20 min) paper presentations, plus one 30-minute session in which the poster authors will briefly present the main features of their posters, which will eventually be interactively discussed in a specific poster session that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Winning entries to the annual Student Low Power Design Contest will also be featured in a separate technical session. Such a rich and strong program would have not been possible without the help of an outstanding Technical Program Committee who worked for weeks reviewing papers and participating in the onsite TPC meeting to select high-quality papers.

Contributors
  • Seoul National University
  • The University of Tokyo
  • Kyushu University
  • Hitachi, Ltd.
  • Polytechnic of Turin

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      Acceptance Rates

      Overall Acceptance Rate 398 of 1,159 submissions, 34%
      YearSubmittedAcceptedRate
      ISLPED '161906032%
      ISLPED '141846334%
      ISLPED '092087235%
      ISLPED '032219041%
      ISLPED '021624025%
      ISLPED '011947338%
      Overall1,15939834%