IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IP core integration into an embedded platform implies the implementation of a customized device driver complying with both the IP communication protocol and the CPU organization (single processor, SMP, AMP). Such a close dependence between driver and ...

Digital microfluidic biochips are being increasingly used for biotechnology applications. The number of control pins used to drive electrodes is a major contributor to the fabrication cost for disposable biochips in a highly cost-sensitive market. Most ...

Placing multiple voltage regulators onto the die is an effective way of enabling distributed on-chip voltage regulation and provides significant benefits in suppressing various types of power supply noise. However, the complex interactions between the ...

3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the ...

To accommodate the ever-growing pin number of complex printed circuit board (PCB) designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component ...

Footprint scaling may reduce wire lengths when more metal layers are available for routing. To achieve optimal wire length, footprint should be very small in which case pin density will be extremely high. However, high pin density may lead to detailed ...

In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of ...

A method for the optimization of the efficiency of alternate tests for adjustable RF mixers is presented in this paper. Alternate tests provide a cost- and time-effective substitute for their conventional specification-based counterparts by attempting ...

Clock-domain crossing (CDC) faults require careful post-silicon testing for multiclock circuits. Even when robust design methods based on synchronizers and design verification techniques are used, process variations can introduce subtle timing problems ...

Galois field arithmetic is a critical component in communication and security-related hardware, requiring dedicated arithmetic architectures for better performance. In many Galois field applications, such as cryptography, the data-path size in the ...

In contrast to structural timing analysis, functional timing analysis for circuit delay computation is accurate, but computationally expensive in refuting false critical paths. Despite recent progress on satisfiability-based functional timing analysis, ...

Automatic macromodeling for passive linear systems is useful in RF/mm-wave circuit designs. Traditional macromodeling approaches only capture the port parameters of the systems, enabling small-signal (AC) and large-signal (transient, PSS, etc) analyses, ...

Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test ...

Functional broadside tests address overtesting of delay faults by using reachable states as scan-in states. Since reachable states are, in general, fully specified, functional broadside tests are not amenable to the commonly used test data compression ...