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Hazard detection by a quinary simulation of logic devices with bounded propagation delays

Author:

Daniel W. LewisAuthors Info & Claims

DAC '72: Proceedings of the 9th Design Automation Workshop

Pages 157 - 164

https://doi.org/10.1145/800153.804941

Published: 26 June 1972 Publication History

Abstract

Effective logic simulation programs must consider device propagation delays to be bounded values. This requires that the logic devices be simulated by models which use a multi-valued logical algebra.

A quinary algebra is developed and employed in special algorithms which not only accurately predict the behavior of a logic circuit for all values of delay, but also detect the possibility of latent hazards and race conditions.

A sample problem is simulated, and conclusions drawn.

References

[1]

Boole, G., "An Investigation of the Laws of Thought", London, 1854 (reprinted by Dover Publications, New York)

Digital Library

[2]

Eichelberger, E.B., "Hazard Detection in Combinational and Sequential Switching Circuits", IBM System Journal, Vol. 9, No. 2, pp. 90-99, March 1965

Digital Library

[3]

Yoeli, M. and Rinon, S., "Application of Ternary Algebra to the Study of Static Hazards", JACM, Vol. 11, No. 1, January 1964, pp. 84-87

Digital Library

[4]

Langdon, G.G., "Analysis of Asynchronous Circuits Under Different Delay Assumptions", IEEE Transactions on Computers, Vol. C-17, No. 12, December 1968, pp. 1131-1143

[5]

Unger, S.H., "Asynchronous Sequential Switching Circuits", Wiley-Interscience, 1969

Digital Library

[6]

pp. 118 (concept of bounded delays)

[7]

pp. 138-139 (consideration and relative importance of rise times)

[8]

pp. 179-183 (ternary logic test for hazards)

[9]

Metze, G.A., "An Application of Multi-valued Logic Systems to Circuits", Proceedings of Symposium on Circuit Analysis, pp. 11-1 through 11-14, University of Illinois, Urbana, 1955

[10]

Muller, D.E., "Treatment of Transition Signals in Electronic Switching Circuits by Algebraic Methods", IRE Transactions on Electronic Computers, Vol. EC-8, No. 3, pp. 401, September 1959

[11]

Jephson, J.S., McQuarrie, R.P., and Vogelsberg, R.E., "A Three-value Computer Design Verification System", IBM System Journal, Vol. 8, No. 3, pp. 178-188, 1969

Digital Library

[12]

Post, E.L., "Introduction to a General Theory of Elementary Propositions", American Journal of Mathematics, Vol. 43, pp. 163-185, 1921

[13]

Lewis, D.W., "Hazard Detection by a Quinary Simulation of Logic Devices with Bounded Propagation Delays", Master's Thesis, Syracuse University, January 1972

[14]

Unger, S.H., "Hazards and Delays in Asynchronous Sequential Switching Circuits", IRE Transactions on Circuit Theory, Vol. CT-6, pp. 12-25, March 1959

[15]

Fantauzzi, Guiseppe, "An Algebraic Model for the Analysis of Logical Circuits", Societa Italiana Telecomunicazioni, Siemans, S.p.A., an unpublished report

Cited By

Guilloud SKunčak V(2022)Equivalence Checking for Orthocomplemented Bisemilattices in Log-Linear TimeTools and Algorithms for the Construction and Analysis of Systems10.1007/978-3-030-99527-0_11(196-214)Online publication date: 2-Apr-2022
https://dl.acm.org/doi/10.1007/978-3-030-99527-0_11
TAKAGI N(2010)A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal OperationsIEICE Transactions on Information and Systems10.1587/transinf.E93.D.2040E93-D:8(2040-2047)Online publication date: 2010
https://doi.org/10.1587/transinf.E93.D.2040
Kang MDeguchi HShirakawa I(2007)A method of hazard detection by five‐valued logic simulation based on the TRF delay modelElectronics and Communications in Japan (Part III: Fundamental Electronic Science)10.1002/ecjc.443075030175:3(1-12)Online publication date: 22-Feb-2007
https://doi.org/10.1002/ecjc.4430750301
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Index Terms

Hazard detection by a quinary simulation of logic devices with bounded propagation delays
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
2. Mathematics of computing
  1. Mathematical analysis
    1. Integral equations

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Published In

cover image ACM Conferences

DAC '72: Proceedings of the 9th Design Automation Workshop

June 1972

406 pages

ISBN:9781450374583

DOI:10.1145/800153

Copyright © 1972 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
IEEE: Institute of Electrical and Electronics Engineers

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 June 1972

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Citations

Cited By

Guilloud SKunčak V(2022)Equivalence Checking for Orthocomplemented Bisemilattices in Log-Linear TimeTools and Algorithms for the Construction and Analysis of Systems10.1007/978-3-030-99527-0_11(196-214)Online publication date: 2-Apr-2022
https://dl.acm.org/doi/10.1007/978-3-030-99527-0_11
TAKAGI N(2010)A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal OperationsIEICE Transactions on Information and Systems10.1587/transinf.E93.D.2040E93-D:8(2040-2047)Online publication date: 2010
https://doi.org/10.1587/transinf.E93.D.2040
Kang MDeguchi HShirakawa I(2007)A method of hazard detection by five‐valued logic simulation based on the TRF delay modelElectronics and Communications in Japan (Part III: Fundamental Electronic Science)10.1002/ecjc.443075030175:3(1-12)Online publication date: 22-Feb-2007
https://doi.org/10.1002/ecjc.4430750301
Hayes J(2006)Digital Simulation with Multiple Logic ValuesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.1986.12701965:2(274-283)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.1986.1270196
Jeong CNowick SMalik SFix LKahng A(2004)Fast hazard detection in combinational circuitsProceedings of the 41st annual Design Automation Conference10.1145/996566.996728(592-595)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996728
Brzozowski JEsik ZIland Y(2001)Algebras for hazard detectionProceedings 31st IEEE International Symposium on Multiple-Valued Logic10.1109/ISMVL.2001.924548(3-12)Online publication date: 2001
https://doi.org/10.1109/ISMVL.2001.924548
Brzozowski J(2000)de Morgan bisemilatticesProceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)10.1109/ISMVL.2000.848616(173-178)Online publication date: 2000
https://doi.org/10.1109/ISMVL.2000.848616
Meijer E(1993)Hazard Algebra and the Design of Asynchronous AutomataFunctional Programming, Glasgow 199210.1007/978-1-4471-3215-8_15(166-177)Online publication date: 1993
https://doi.org/10.1007/978-1-4471-3215-8_15
Vaughn GHumcke DGaley JSzygenda SPistilli PDooner NBrinsfield JOlila J(1976)CDALGO - a test pattern generation programProceedings of the 13th Design Automation Conference10.1145/800146.804813(186-193)Online publication date: 28-Jun-1976
https://dl.acm.org/doi/10.1145/800146.804813
Mor M(1976)On the Three-Valued Simulation of Digital SystemsIEEE Transactions on Computers10.1109/TC.1976.167457125:11(1152-1156)Online publication date: 1-Nov-1976
https://dl.acm.org/doi/10.1109/TC.1976.1674571
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