A recursive technique for generating exhaustive patterns is presented. The method is optimal, i.e., in one experiment it covers exhaustively every block of k adjacent inputs in the first 2/sup k/ vectors. Implementation methods based on characteristic ...
In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot ...
A low transition test pattern generator, called LT-LFSR, is proposed to reduce the average and peak power of a circuit during test by reducing the transitions among patterns. Transitions are reduced in two dimensions; 1) between consecutive patterns (...
Association for Computing Machinery
New York, NY, United States
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in