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Article

A design space exploration framework for reduced bit-width instruction set architecture (rISA) design

Authors:

Aviral Shrivastava,

Alex NicolauAuthors Info & Claims

ISSS '02: Proceedings of the 15th international symposium on System Synthesis

Pages 120 - 125

https://doi.org/10.1145/581199.581228

Published: 02 October 2002 Publication History

Abstract

Code size is a critical concern in many embedded system applications, especially those using RISC cores. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, space-efficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature (termed rISA) can potentially reduce the code size by up to 50% with minimal performance degradation. However, contemporary processors incorporate only a simple rISA feature with severe restrictions on register accessibility. We present a compiler-in-the-loop Design Space Exploration framework that is capable of exploring various interesting rISA designs. We also present experimental results using this framework and show rISA designs that improve on the code size reduction obtained by existing rISA architectures.

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Digital Library

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A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau. An efficient compiler technique for code size reduction using reduced bit-width isas. In Proc. of Design Automation and Test in Europe, 2002.]]

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A. Halambi, A. Shrivastava, N. Dutt, and A. Nicolau. A customizable compiler framework for embedded systems. In SCOPES, 2001.]]

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Cited By

Lozano HIto M(2016)Increasing the Code Density of Embedded RISC Applications2016 IEEE 19th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2016.33(182-189)Online publication date: May-2016
https://doi.org/10.1109/ISORC.2016.33
Shrivastava ADutt N(2009)Compiler-Aided Design of Embedded ComputersThe Compiler Design Handbook10.1201/9781420043839.ch3(3-1-3-36)Online publication date: 7-Dec-2009
https://doi.org/10.1201/9781420043839.ch3
Weaver VMcKee S(2009)Code density concerns for new architectures2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413117(459-464)Online publication date: Oct-2009
https://doi.org/10.1109/ICCD.2009.5413117
Show More Cited By

Index Terms

A design space exploration framework for reduced bit-width instruction set architecture (rISA) design
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing

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Information & Contributors

Information

Published In

cover image ACM Conferences

ISSS '02: Proceedings of the 15th international symposium on System Synthesis

October 2002

278 pages

ISBN:1581135769

DOI:10.1145/581199

General Chair:
El Mostapha Aboulhamid
University of Montreal, Canada
,
Program Chair:
Yukihiro Nakamura
Kyoto University, Japan

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\DATC: IEEE Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 October 2002

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Sponsor:

ACM
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IEEE-CS\DATC

ISSS02: 15th International Symposium on System Synthesis

October 2 - 4, 2002

Kyoto, Japan

Acceptance Rates

ISSS '02 Paper Acceptance Rate 38 of 71 submissions, 54%;

Overall Acceptance Rate 38 of 71 submissions, 54%

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Cited By

Lozano HIto M(2016)Increasing the Code Density of Embedded RISC Applications2016 IEEE 19th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2016.33(182-189)Online publication date: May-2016
https://doi.org/10.1109/ISORC.2016.33
Shrivastava ADutt N(2009)Compiler-Aided Design of Embedded ComputersThe Compiler Design Handbook10.1201/9781420043839.ch3(3-1-3-36)Online publication date: 7-Dec-2009
https://doi.org/10.1201/9781420043839.ch3
Weaver VMcKee S(2009)Code density concerns for new architectures2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413117(459-464)Online publication date: Oct-2009
https://doi.org/10.1109/ICCD.2009.5413117
Shrivastava ASanghyun PEarlie EDutt NNicolau AYunheung P(2007)Automatic Design Space Exploration of Register Bypasses in Embedded ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2007.90706626:12(2102-2115)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1109/TCAD.2007.907066
Liu XZhang JCheng X(2007)NISDProceedings of the 3rd international conference on Embedded Software and Systems10.1007/978-3-540-72685-2_26(271-282)Online publication date: 14-May-2007
https://dl.acm.org/doi/10.1007/978-3-540-72685-2_26

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