PARE: instruction set architecture for efficient code size reduction
YJ Kwon, X Ma, HJ Lee - Electronics Letters, 1999 - IET
YJ Kwon, X Ma, HJ Lee
Electronics Letters, 1999•IETTo achieve efficient code size reduction, a new instruction set architecture and a register
allocation technique optimised for the architecture are proposed. Experiments show that the
efficiency of the code size reduction is improved by an average of 13.8% when compared
with that for the conventional approach.
allocation technique optimised for the architecture are proposed. Experiments show that the
efficiency of the code size reduction is improved by an average of 13.8% when compared
with that for the conventional approach.
To achieve efficient code size reduction, a new instruction set architecture and a register allocation technique optimised for the architecture are proposed. Experiments show that the efficiency of the code size reduction is improved by an average of 13.8% when compared with that for the conventional approach.
IET