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COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures

Published: 30 January 2019 Publication History

Abstract

FPGAs are becoming more heteregeneous to better adapt to different markets, motivating rapid exploration of different blocks/tiles for FPGAs. To evaluate a new FPGA architectural idea, one should be able to accurately obtain the area, delay, and energy consumption of the block of interest. However, current FPGA circuit design tools can only model simple, homogeneous FPGA architectures with basic logic blocks and also lack DSP and other heterogeneous block support. Modern FPGAs are instead composed of many different tiles, some of which are designed in a full custom style and some of which mix standard cell and full custom styles.
To fill this modelling gap, we introduce COFFE 2, an open-source FPGA design toolset for automatic FPGA circuit design. COFFE 2 uses a mix of full custom and standard cell flows and supports not only complex logic blocks with fracturable lookup tables and hard arithmetic but also arbitrary heterogeneous blocks. To validate COFFE 2 and demonstrate its features, we design and evaluate a multi-mode Stratix III-like DSP block and several logic tiles with fracturable LUTs and hard arithmetic. We also demonstrate how COFFE 2’s interface to VTR allows full evaluation of block-routing interfaces and various fracturable 6-LUT architectures.

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Information

Published In

cover image ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems  Volume 12, Issue 1
March 2019
115 pages
ISSN:1936-7406
EISSN:1936-7414
DOI:10.1145/3310278
  • Editor:
  • Deming Chen
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 January 2019
Accepted: 01 December 2018
Revised: 01 October 2018
Received: 01 April 2018
Published in TRETS Volume 12, Issue 1

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Author Tags

  1. FPGA
  2. architecture exploration
  3. automatic circuit design

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  • Research-article
  • Research
  • Refereed

Funding Sources

  • NSERC/Intel Industrial Research Chair in Programmable Silicon
  • Huawei

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  • (2024)Towards High-Throughput Neural Network Inference with Computational BRAM on Nonvolatile FPGAs2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546738(1-6)Online publication date: 25-Mar-2024
  • (2024)An Efficient FPGA Architecture with Turn-Restricted Switch BoxesACM Transactions on Design Automation of Electronic Systems10.1145/364380929:3(1-18)Online publication date: 3-Feb-2024
  • (2024)An Open-Source Tool to Model and Explore Complex Routing Architecture for FPGA2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617494(734-739)Online publication date: 10-May-2024
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  • (2023)Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD ResearchIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.327258242:11(3895-3909)Online publication date: 1-Nov-2023
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