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FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures

Authors:

Manana Lortkipanidze,

Paolo IenneAuthors Info & Claims

FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 80 - 89

https://doi.org/10.1145/2847263.2847280

Published: 21 February 2016 Publication History

Abstract

In theory, tools like VTR---a retargetable toolchain mapping circuits onto easily-described hypothetical FPGA architectures---could play a key role in the development of wildly innovative FPGA architectures. In practice, however, the experiments that one can conduct with these tools are severely limited by the ability of FPGA architects to produce reliable delay and area models---these depend on transistor-level design techniques which require a different set of skills. In this paper, we introduce a novel approach, which we call Fpresso, to model the delay and area of a wide range of largely different FPGA architectures quickly and with reasonable accuracy. We take inspiration from the way a standard-cell flow performs large scale transistor-size optimization and apply the same concepts to FPGAs, only at a coarser granularity. Skilled users prepare for \fpresso locally optimized libraries of basic components with a variety of driving strengths. Then, ordinary users specify arbitrary FPGA architectures as interconnects of basic components. This is globally optimized within minutes through an ordinary logic synthesis tool which chooses the most fitting version of each cell and adds buffers wherever appropriate. The resulting delay and area characteristics can be automatically used for VTR. Our results show that \fpresso provides models that are on average within some 10-20\% of those by a state-of-the-art FPGA optimization tool and is orders of magnitude faster. Although the modelling error may appear relatively high,we show that it seldom results in misranking a set of architectures, thus indicating a reasonable modeling faithfulness.

References

[1]

I. Ahmadpour, B. Khaleghi, and H. Asadi. An efficient reconfigurable architecture by characterizing most frequent logic functions. In Proceedings of the 25th International Conference on Field-Programmable Logic and Applications, 2015.

[2]

E. Ahmed and J. Rose. The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Transactions on Very Large Scale Integration Systems, 12(3):288--298, 2004.

Digital Library

[3]

C.-P. Chen, C. C. Chu, and D. Wong. Fast and exact simultaneous gate and wire sizing by lagrangian relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(7):1014--1025, 1999.

Digital Library

[4]

C. Chiasson and V. Betz. COFFE: Fully-automated transistor sizing for FPGAs. In Proceedings of the IEEE International Conference on Field Programmable Technology, pages 34--41, 2013.

[5]

D. Chinnery and K. Keutzer. Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design. Springer US, New York, NY., 2002.

[6]

H. Eriksson, P. Larsson-Edefors, T. Henriksson, and C. Svensson. Full-custom vs. standard-cell design flow: an adder case study. In Proceedings of the Asia and South Pacific Design Automation Conference, pages 507--510, 2003.

Digital Library

[7]

J. P. Fishburn and A. E. Dunlop. TILOS: A posynomial programming approach to transistor sizing. In The Best of ICCAD, pages 295--302. Springer, 2003.

[8]

N. P. Jouppi, A. B. Kahng, N. Muralimanohar, and V. Srinivas. CACTI-IO: CACTI with OFF-chip power-area-timing models. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VLSI-23(7):1254--67, July 2015.

[9]

K. Kasamsetty, M. Ketkar, and S. S. Sapatnekar. A new class of convex functions for delay modeling and its application to the transistor sizing problem {CMOS gates}. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(7):779--788, 2000.

Digital Library

[10]

J. H. Kim and J. H. Anderson. Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. In Proceedings of the 25th International Conference on Field-Programmable Logic and Applications, 2015.

[11]

I. Kuon and J. Rose. Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design. IEEE Transactions on Very Large Scale Integration Systems, 19(1):71--84, 2011.

Digital Library

[12]

D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cliff, and J. Rose. The Stratix II logic and routing architecture. In Proceedings of the 13th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 14--20, Monterey, Calif., Feb. 2005.

Digital Library

[13]

D. Lewis, E. Ahmed, D. Cashman, T. Vanderhoek, C. Lane, A. Lee, and P. Pan. Architectural enhancements in Stratix-III#8482; and Stratix-IV#8482;. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '09, pages 33--42, New York, NY, USA, 2009. ACM.

Digital Library

[14]

N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi. CACTI 6.0: A tool to model large caches. Technical Report HPL-2009-85, Hewlett-Packard Development Company, Palo Alto, Calif., Apr. 2009.

[15]

H. Parandeh-Afshar, H. Benbihi, D. Novo, and P. Ienne. Rethinking FPGAs: Elude the flexibility excess of LUTs with And-Inverter Cones. In Proceedings of the 20th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 119--28, Monterey, Calif., Feb. 2012.

Digital Library

[16]

J. Rose, J. Luu, C. W. Yu, O. Densmore, J. Goeders, A. Somerville, K. B. Kent, P. Jamieson, and J. Anderson. The VTR project: architecture and CAD for FPGAs from Verilog to routing. In Proceedings of the 20th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 77--86, 2012.

Digital Library

[17]

V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi. Fast and exact transistor sizing based on iterative relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(5):568--581, 2002.

Digital Library

[18]

S. J. Wilton and N. P. Jouppi. An enhanced access and cycle time model for on-chip caches. Technical Report WRL-93-5, Digital Equipment Corporation, Palo Alto, Calif., July 1994.

Cited By

Nikolić SNikolić S(2025)Modeling Programmable Routing in Advanced TechnologiesModern Programmable Interconnect Design10.1007/978-3-031-80629-2_4(73-119)Online publication date: 7-Mar-2025
https://doi.org/10.1007/978-3-031-80629-2_4
Al-Qawasmi MYe A(2023)Estimating Post-Synthesis Area, Delay, and Leakage Power of Standard Cell Based FPGA Tiles2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE58730.2023.10289025(117-123)Online publication date: 24-Sep-2023
https://doi.org/10.1109/CCECE58730.2023.10289025
Long HBai YLi YWang JLai J(2023)Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396538(1-4)Online publication date: 24-Oct-2023
https://doi.org/10.1109/ASICON58565.2023.10396538
Show More Cited By

Index Terms

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures
1. Hardware
  1. Electronic design automation
    1. Modeling and parameter extraction
    2. Physical design (EDA)
  2. Integrated circuits
    1. Digital switches
      1. Transistors
    2. Reconfigurable logic and FPGAs
      1. Programmable interconnect
      2. Programmable logic elements

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Information

Published In

cover image ACM Conferences

FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2016

298 pages

ISBN:9781450338561

DOI:10.1145/2847263

General Chair:
Deming Chen
University of Illinois at Urbana-Champaign, USA
,
Program Chair:
Jonathan Greene
Microsemi, USA

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 February 2016

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FPGA'16: The 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 21 - 23, 2016

California, Monterey, USA

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FPGA '16 Paper Acceptance Rate 20 of 111 submissions, 18%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Nikolić SNikolić S(2025)Modeling Programmable Routing in Advanced TechnologiesModern Programmable Interconnect Design10.1007/978-3-031-80629-2_4(73-119)Online publication date: 7-Mar-2025
https://doi.org/10.1007/978-3-031-80629-2_4
Al-Qawasmi MYe A(2023)Estimating Post-Synthesis Area, Delay, and Leakage Power of Standard Cell Based FPGA Tiles2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE58730.2023.10289025(117-123)Online publication date: 24-Sep-2023
https://doi.org/10.1109/CCECE58730.2023.10289025
Long HBai YLi YWang JLai J(2023)Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396538(1-4)Online publication date: 24-Oct-2023
https://doi.org/10.1109/ASICON58565.2023.10396538
Li YZhang YLiu JGong JWang JLai JTao XQu G(2022)AutoTEAIntegration, the VLSI Journal10.1016/j.vlsi.2022.06.01087:C(231-240)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.06.010
Ahmed IShen LBetz V(2020)Optimizing FPGA Logic Circuitry for Variable Voltage SuppliesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.296250128:4(890-903)Online publication date: Apr-2020
https://doi.org/10.1109/TVLSI.2019.2962501
Khaleghi BSalamat SRosing T(2020)Revisiting FPGA Routing under Varying Operating Conditions2020 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT51103.2020.00022(94-102)Online publication date: Dec-2020
https://doi.org/10.1109/ICFPT51103.2020.00022
Yazdanshenas SBetz V(2019)COFFE 2ACM Transactions on Reconfigurable Technology and Systems10.1145/330129812:1(1-27)Online publication date: 30-Jan-2019
https://dl.acm.org/doi/10.1145/3301298
Li ZXiao YZhang YPang YHu CWang JLai JHomayoun HTaskin BMohsenin TZhao W(2019)An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits OptimizationProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318003(93-98)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318003
Ahmed IShen LBetz V(2019)Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00011(1-8)Online publication date: Sep-2019
https://doi.org/10.1109/FPL.2019.00011
Xu JLi ZPang YWang JQu GLai J(2019)Research on the impact of different benchmark circuits on the representative path in FPGAs2019 IEEE 13th International Conference on ASIC (ASICON)10.1109/ASICON47005.2019.8983550(1-3)Online publication date: Oct-2019
https://doi.org/10.1109/ASICON47005.2019.8983550
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