Contemporary FPGAs are composed of a mix of full custom and standard cell-based circuitry, organized into many heterogeneous blocks and the programmable routing. To explore new FPGA architectures, in particular those incorporating new hard blocks, we must estimate the area, power and delay of any new block of interest, and would like to do so efficiently so that many ideas can be evaluated. Unfortunately, existing open source academic FPGA circuit modelling tools cannot target such a wide range of blocks and cannot mix custom and standard cell circuitry. In this work, we present an enhanced (hybrid) COFFE flow that automatically optimizes and models a wide variety of blocks using an intelligent mix of full custom transistor sizing and standard cell flows. Hybrid COFFE can generate models for both advanced logic blocks enriched with hard arithmetic and fracturable LUTs using its full custom flow and arbitrary hard blocks (such as DSP blocks) described in standard Hardware Description Languages (HDLs) that are fabricated using a mix of standard cell and full custom flows. To validate this hybrid flow we model a Stratix-III like DSP block in 65 nm CMOS and find good agreement with published commercial data. The resulting block and routing models are output in the Verilog-To-Routing (VTR) architecture format to facilitate architectural exploration of advanced FPGA blocks.