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Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration

Authors:

Gabriel Busnot,

Tanguy Sassolas,

Nicolas VentrouxAuthors Info & Claims

RAPIDO '19: Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools

Article No.: 3, Pages 1 - 8

https://doi.org/10.1145/3300189.3300192

Published: 21 January 2019 Publication History

Abstract

Virtual Prototyping has been widely adopted as a cost-effective solution for early hardware and software co-validation. However, as systems grow in complexity and scale, both the time required to get to a correct virtual prototype, and the time required to run real software on it can quickly become unmanageable. This paper introduces a feature-rich integrated virtual prototyping solution, designed to meet industrial needs not only in terms of performance, but also in terms of ease, rapidity and automation of modelling and exploration. It introduces novel methods to leverage the QEMU dynamic binary translator and the abstraction levels offered by SystemC/TLM 2.0 to provide the best possible trade-offs between accuracy and performance at all steps of the design. The solution also ships with a dynamic platform composition infrastructure that makes it possible to model and explore a myriad of architectures using a compact high-level description. Results obtained simulating a RISC-V SMP architecture running the PARSEC benchmark suite reveal that simulation speed can range from 30 MIPS in accurate simulation mode to 220 MIPS in fast functional validation mode.

References

[1]

TLM 2.0. 2018. Open SystemC Initiative (OSCI). https://www.accellera.org/images/downloads/standards/systemc/TLM_2_0_LRM.pdf

[2]

QEMU Memory API. 2018. QEMU. https://github.com/qemu/qemu/blob/master/docs/devel/memory.txt.

[3]

D. August, J. Chang, S. Girbal, D. Gracia-Perez, G. Mouchard, D. A. Penry, O. Temam, and N. Vachharajani. 2007. UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development. IEEE Computer Architecture Letters (2007), 45--48.

Digital Library

[4]

Fabrice Bellard. 2005. QEMU, a fast and portable dynamic translator. In USENIX Annual Technical Conference (ATEC). Anaheim, CA, 41--41.

Digital Library

[5]

Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. 2008. The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical Report TR-811-08. Princeton University.

[6]

Andrew Waterman et al. 2014. The RISC-V Instruction Set Manual.

[7]

Binkert et al. 2011. The gem5 simulator. ACM SIGARCH Computer Architecture News 39, 2 (2011), 1--7.

Digital Library

[8]

Blochwitz et al. 2012. Functional mockup interface 2.0: The standard for tool independent exchange of simulation models. In International MODELICA Conference (MODELICA). Munich, DE, 173--184.

[9]

Chiang et al. 2011. A QEMU and SystemC-based cycle-accurate ISS for performance estimation on SoC development. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 4 (2011), 593--606.

Digital Library

[10]

Guillaume Delbergue et al. 2016. QBox: an industrial solution for virtual platform simulation using QEMU and SystemC TLM-2.0. In European Congress on Embedded Real Time Software and Systems (ERTS). Toulouse, FR, 315--324.

[11]

Kraemer et al. 2009. A checkpoint/restore framework for SystemC-based virtual platforms. In International Symposium on System-on-Chip (SOC). IEEE, Tampere, FI, 161--167.

Digital Library

[12]

Monton et al. 2007. Mixed sw/systemc soc emulation framework. In IEEE International Symposium on Industrial Electronics (ISIE). Vigo, ES, 2338--2341.

[13]

Montón et al. 2009. Mixed simulation kernels for high performance virtual platforms. In Forum on Specification & Design Languages (FDL). Munich, DE, 1--6.

[14]

Màrius Montón et al. 2013. Checkpointing for virtual platforms and SystemC-TLM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, 1 (2013), 133--141.

Digital Library

[15]

M Gligor, N Fournel, and F Pétrot. 2009. Using Binary Translation in Event Driven Simulation for Fast and Flexible MPSoC Simulation. In International Conference on Hardware-Software Codesign and System Synthesis (CODES+ ISSS). Grenoble, FR, 71--80.

Digital Library

[16]

C. Menard, J. Castrillon, M. Jung, and N. Wehn. 2017. System Simulation with gem5 and SystemC. In International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). Samos, GR, 62--69.

[17]

Open Virtual Platforms (OVP). 2018. Imperas Ltd. http://www.ovpworld.org

[18]

Virtual System Platform. 2018. Cadence. https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/Archive/virtual_system_platform_ds.pdf

[19]

Vista Virtual Prototyping. 2018. Mentor, A Siemens Business. https://www.mentor.com/esl/vista/virtual-prototyping/

[20]

N Rodman. 2008. ARM fast models-virtual platforms for embedded software development. Information Quarterly Magazine 7, 4 (2008), 33--36.

[21]

Rusty Russell. 2008. virtio: towards a de-facto standard for virtual I/O devices. ACM SIGOPS Operating Systems Review 42, 5 (2008), 95--103.

Digital Library

[22]

Simics. 2018. Wind River. http://www.windriver.com/products/simics

[23]

TLMu. 2018. Edgar E. Iglesias. https://edgarigl.github.io/tlmu/tlmu.pdf

[24]

N. Ventroux, A. Guerre, T. Sassolas, L. Moutaoukil, G. Blanc, C. Bechara, and R. David. 2010. SESAM: An MPSoC Simulation Environment for Dynamic Application Processing. In IEEE International Conference on Computer and Information Technology (CIT). Bradford, UK, 1880--1886.

Digital Library

[25]

Virtualizer. 2018. Synopsys. https://www.synopsys.com/verification/virtual-prototyping/virtualizer.html

[26]

VLAB. 2018. ASTC. http://vlabworks.com/index.php/products/

Cited By

Schätzle FFalquez CHeinen SHo NPortero ASuarez EVan Den Boom JVan Waasen S(2024)Modeling methodology for multi-die chip design based on gem5/SystemC co-simulationProceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design10.1145/3642921.3642956(35-41)Online publication date: 18-Jan-2024
https://dl.acm.org/doi/10.1145/3642921.3642956
Fu VZaourar LMunier-Kordon ADuranton M(2024)Design Space Exploration of HPC Systems with Random Forest-based Bayesian OptimizationProceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design10.1145/3642921.3642923(9-15)Online publication date: 18-Jan-2024
https://dl.acm.org/doi/10.1145/3642921.3642923
Alam TRamaiah IRay S(2024)VirSoC: Automatic Synthesis of Virtual System-on-Chip EnvironmentsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339855843:12(4426-4438)Online publication date: Dec-2024
https://doi.org/10.1109/TCAD.2024.3398558
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Published In

cover image ACM Other conferences

RAPIDO '19: Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools

January 2019

44 pages

ISBN:9781450362603

DOI:10.1145/3300189

Conference Chair:
Daniel Chillet
University of Rennes 1

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2019

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RAPIDO '19

RAPIDO '19: Methods and Tools

January 21 - 23, 2019

Valencia, Spain

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Overall Acceptance Rate 14 of 28 submissions, 50%

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Cited By

Schätzle FFalquez CHeinen SHo NPortero ASuarez EVan Den Boom JVan Waasen S(2024)Modeling methodology for multi-die chip design based on gem5/SystemC co-simulationProceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design10.1145/3642921.3642956(35-41)Online publication date: 18-Jan-2024
https://dl.acm.org/doi/10.1145/3642921.3642956
Fu VZaourar LMunier-Kordon ADuranton M(2024)Design Space Exploration of HPC Systems with Random Forest-based Bayesian OptimizationProceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design10.1145/3642921.3642923(9-15)Online publication date: 18-Jan-2024
https://dl.acm.org/doi/10.1145/3642921.3642923
Alam TRamaiah IRay S(2024)VirSoC: Automatic Synthesis of Virtual System-on-Chip EnvironmentsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339855843:12(4426-4438)Online publication date: Dec-2024
https://doi.org/10.1109/TCAD.2024.3398558
Özkaya ÖÖrs B(2024)Model-based, fully simulated, system-level power consumption estimation of IoT devicesMicroprocessors and Microsystems10.1016/j.micpro.2024.105009105(105009)Online publication date: Mar-2024
https://doi.org/10.1016/j.micpro.2024.105009
Zaourar LBenazouz MMouhagir AFalquez CPortero AHo NSuarez EPetrakis PMarazakis MSgherzi FFernandez IDolbeau RPleiter D(2024)Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPCArchitecture of Computing Systems10.1007/978-3-031-66146-4_17(251-265)Online publication date: 1-Aug-2024
https://doi.org/10.1007/978-3-031-66146-4_17
Krishnakumar AOgras UMarculescu RKishinevsky MMudge T(2023)Domain-Specific Architectures: Research Problems and Promising ApproachesACM Transactions on Embedded Computing Systems10.1145/356394622:2(1-26)Online publication date: 24-Jan-2023
https://dl.acm.org/doi/10.1145/3563946
Zheng XWu JLin XGao HCai SXiong X(2023)Hardware/Software Co-Design of Cryptographic SoC Based on RISC-V Virtual PrototypeIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.326718670:9(3624-3628)Online publication date: Sep-2023
https://doi.org/10.1109/TCSII.2023.3267186
Zaourar LChillet APhilippe J(2023)A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors2023 26th Euromicro Conference on Digital System Design (DSD)10.1109/DSD60849.2023.00108(756-763)Online publication date: 6-Sep-2023
https://doi.org/10.1109/DSD60849.2023.00108
Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2023)Eine Open-Source RISC-V EvaluierungsplattformVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_3(21-62)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-18174-0_3
Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2023)EinführungVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_1(1-10)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-18174-0_1
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