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research-article

ACED: a hardware library for generating DSP systems

Authors:

Adam Izraelevitz,

Jonathan Bachrach,

Borivoje NikolićAuthors Info & Claims

DAC '18: Proceedings of the 55th Annual Design Automation Conference

Article No.: 61, Pages 1 - 6

https://doi.org/10.1145/3195970.3195981

Published: 24 June 2018 Publication History

Abstract

Designers translate DSP algorithms into application-specific hardware via primitives composed in various ways for different architectural realizations. Despite sharing underlying algorithms and hardware constructs, designs are often difficult to reuse, leading to redeveloping/reverifying conceptually similar instances. Hardware generators are attractive solutions for effectively balancing fine-grained control of implementation details with simple, retargetable hardware descriptions. This work presents ACED, a hardware library for generating DSP systems. It extends the Chisel hardware construction language and FIRRTL compiler and operates on three principles: zero-cost abstraction, unobtrusive downstream optimization/specialization promoting generator reusability, and unified, portable systems modeling and verification.

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J. Bachrach, et al. 2012. Chisel: Constructing hardware in a Scala embedded language. In Proc. IEEE/EDAC/ACM DAC. 1212--1221.

Digital Library

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Cited By

A S APatil AS KGowda KN A N(2023)Efficient Implementation of Lookup Table-Based Numerically Controlled Oscillator2023 7th International Conference on Design Innovation for 3 Cs Compute Communicate Control (ICDI3C)10.1109/ICDI3C61568.2023.00022(71-75)Online publication date: 2-Nov-2023
https://doi.org/10.1109/ICDI3C61568.2023.00022
Dai YLaCaille GLiew HDunn JNikolic B(2021)A Scalable Massive MIMO Uplink Baseband Processing GeneratorICC 2021 - IEEE International Conference on Communications10.1109/ICC42927.2021.9500566(1-6)Online publication date: Jun-2021
https://doi.org/10.1109/ICC42927.2021.9500566
Bailey SRigge PHan JLin RChang EMao HWang ZMarkley CIzraelevitz AWang ANarevsky NBae WShauck SMontano SNorsworthy JRazzaque MMa WLentiro ADoerflein MHeckendorn DMcGrath JDeSeta FShoham RStellfox MSnowden MCole JFuhrman DRichards BBachrach JAlon ENikolic B(2019)A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET InstanceIEEE Journal of Solid-State Circuits10.1109/JSSC.2019.292409054:10(2786-2801)Online publication date: Oct-2019
https://doi.org/10.1109/JSSC.2019.2924090
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Index Terms

ACED: a hardware library for generating DSP systems
1. Hardware

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Published In

cover image ACM Conferences

DAC '18: Proceedings of the 55th Annual Design Automation Conference

June 2018

1089 pages

ISBN:9781450357005

DOI:10.1145/3195970

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 June 2018

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DARPA CRAFT program
NSF-GRFP
ADEPT (Intel iSTC on Agile Design)
BWRC

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DAC '18

Sponsor:

EDAC
SIGDA

DAC '18: The 55th Annual Design Automation Conference 2018

June 24 - 29, 2018

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

A S APatil AS KGowda KN A N(2023)Efficient Implementation of Lookup Table-Based Numerically Controlled Oscillator2023 7th International Conference on Design Innovation for 3 Cs Compute Communicate Control (ICDI3C)10.1109/ICDI3C61568.2023.00022(71-75)Online publication date: 2-Nov-2023
https://doi.org/10.1109/ICDI3C61568.2023.00022
Dai YLaCaille GLiew HDunn JNikolic B(2021)A Scalable Massive MIMO Uplink Baseband Processing GeneratorICC 2021 - IEEE International Conference on Communications10.1109/ICC42927.2021.9500566(1-6)Online publication date: Jun-2021
https://doi.org/10.1109/ICC42927.2021.9500566
Bailey SRigge PHan JLin RChang EMao HWang ZMarkley CIzraelevitz AWang ANarevsky NBae WShauck SMontano SNorsworthy JRazzaque MMa WLentiro ADoerflein MHeckendorn DMcGrath JDeSeta FShoham RStellfox MSnowden MCole JFuhrman DRichards BBachrach JAlon ENikolic B(2019)A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET InstanceIEEE Journal of Solid-State Circuits10.1109/JSSC.2019.292409054:10(2786-2801)Online publication date: Oct-2019
https://doi.org/10.1109/JSSC.2019.2924090
Wang ABae WHan JBailey SOcal ORigge PWang ZRamchandran KAlon ENikolic B(2019)A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFETIEEE Journal of Solid-State Circuits10.1109/JSSC.2019.291309954:7(1993-2008)Online publication date: Jul-2019
https://doi.org/10.1109/JSSC.2019.2913099
Nikolic BAlon EAsanovic K(2018)Generating the Next Wave of Custom SiliconESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)10.1109/ESSCIRC.2018.8494310(6-11)Online publication date: Sep-2018
https://doi.org/10.1109/ESSCIRC.2018.8494310

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