Partitioning signal processing applications to different granularity reconfigurable logic

In this paper, we propose a methodology for partitioning DSP applications between the fine and coarse-grain reconfigurable hardware for improving performance. The fine-grain logic is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware, a 2-Dimensional array of Processing Elements is considered. These different granularity reconfigurable functional units are embedded in a hybrid platform. The proposed methodology mainly consists of three steps, the analysis, the mapping onto the coarse-grain reconfigurable array, and the mapping onto the fine-grain reconfigurable hardware. The experiments for five real-world applications show that the speedup, relative to an all-FPGA solution, ranges from 1.4 to 3.1 for the considered applications.