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A Novel Polymorphic Gate Based Circuit Fingerprinting Technique

Authors:

Timothy Dunlap,

Xiaole CuiAuthors Info & Claims

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

Pages 141 - 146

https://doi.org/10.1145/3194554.3194572

Published: 30 May 2018 Publication History

Abstract

Polymorphic gates are reconfigurable devices that deliver multiple functionalities at different temperature, supply voltage or external inputs. Capable of working in different modes, polymorphic gate is a promising candidate for embedding secret information such as fingerprints. In this paper we report five polymorphic gates whose functionality varies in response to specific control input and propose a circuit fingerprinting scheme based on these gates. The scheme selectively replaces standard logic cells by polymorphic gates whose functionality differs with the standard cells only on Satisfiability Don't Care conditions. Additional dummy fingerprint bits are also introduced to enhance the fingerprint's robustness against attacks such as fingerprint removal and modification. Experimental results on ISCAS and MCNC benchmark circuits demonstrate that our scheme introduces low overhead. More specifically, the average overhead in area, speed and power are 4.04%, 6.97% and 4.15% respectively when we embed 64-bit fingerprint that consists of 32 real fingerprint bits and 32 dummy bits. This is only half of the overhead of the other known approach when they create 32-bit fingerprints.

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Cited By

Dunlap TQu G(2024)Enhancing Subthreshold Stuck-at Fault Testing with Polymorphic Gates2024 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia62534.2024.10661314(1-6)Online publication date: 18-Aug-2024
https://doi.org/10.1109/ITC-Asia62534.2024.10661314
Dunlap TLu ZQu GKim T(2024)Towards Finding the Sources of Polymorphism in Polymorphic Gates (Invited)Proceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473830(319-324)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473830
Kumar RDivyanshu DKhan DAmara SMassoud Y(2023)Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security ApplicationsElectronics10.3390/electronics1204090212:4(902)Online publication date: 10-Feb-2023
https://doi.org/10.3390/electronics12040902
Show More Cited By

Index Terms

A Novel Polymorphic Gate Based Circuit Fingerprinting Technique
1. Hardware
  1. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Evolvable hardware
2. Security and privacy
  1. Security services
    1. Digital rights management

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Information

Published In

cover image ACM Conferences

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

May 2018

533 pages

ISBN:9781450357241

DOI:10.1145/3194554

General Chair:
Deming Chen
University of Illinois, USA
,
Program Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
IEEE CASS

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 May 2018

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National Science Foundation

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GLSVLSI '18

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SIGDA

GLSVLSI '18: Great Lakes Symposium on VLSI 2018

May 23 - 25, 2018

IL, Chicago, USA

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GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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GLSVLSI '25

Sponsor:
sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

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Cited By

Dunlap TQu G(2024)Enhancing Subthreshold Stuck-at Fault Testing with Polymorphic Gates2024 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia62534.2024.10661314(1-6)Online publication date: 18-Aug-2024
https://doi.org/10.1109/ITC-Asia62534.2024.10661314
Dunlap TLu ZQu GKim T(2024)Towards Finding the Sources of Polymorphism in Polymorphic Gates (Invited)Proceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473830(319-324)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473830
Kumar RDivyanshu DKhan DAmara SMassoud Y(2023)Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security ApplicationsElectronics10.3390/electronics1204090212:4(902)Online publication date: 10-Feb-2023
https://doi.org/10.3390/electronics12040902
Chen YCui XYang PQu G(2023)An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323780(01-09)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323780
Sun YCui XChen YCui X(2021)The logic obfuscation of LFSR with the crosstalk based polymorphic gate2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST53231.2021.9699592(1-6)Online publication date: 16-Dec-2021
https://doi.org/10.1109/AsianHOST53231.2021.9699592
Dunlap TAramoon OQu GWang TCui XYu D(2021)A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST53231.2021.9699513(1-4)Online publication date: 16-Dec-2021
https://doi.org/10.1109/AsianHOST53231.2021.9699513
Dunlap TQu GLai J(2019)A Polymorphic Circuit Interoperability Framework2019 IEEE 13th International Conference on ASIC (ASICON)10.1109/ASICON47005.2019.8983594(1-4)Online publication date: Oct-2019
https://doi.org/10.1109/ASICON47005.2019.8983594

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