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Design methodologies for partially reconfigured systems

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J. D. HadleyAuthors Info & Claims

FCCM '95: Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines

Page 78

Published: 19 April 1995 Publication History

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Abstract: Run time reconfiguration (RTR) as an implementation approach that divides an application into a series of sequentially executed stages with each stage implemented as a separate circuit module. Partial RTR extends this approach by partitioning these stages and designing their circuit modules such that they exhibit a high degree of functional and physical commonality. Transitioning between configurations can then be accomplished by updating only the differences between configurations. This reduces the amount of time that an RTR application spends configuring and significantly enhances overall performance. The paper presents the design methodology for partial RTR in the context of RRANN2, a partial RTR artificial neural network.

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Cited By

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Neely CBrebner GShang W(2013)ReShapeACM Transactions on Reconfigurable Technology and Systems10.1145/2457443.24574486:1(1-23)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1145/2457443.2457448
El-Araby EGonzalez IEl-Ghazawi T(2009)Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable ComputingACM Transactions on Reconfigurable Technology and Systems10.1145/1462586.14625901:4(1-23)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1145/1462586.1462590
El-Araby EGonzalez IEl-Ghazawi TKindratenko VEl-Ghazawi T(2007)Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computingProceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC0710.1145/1328554.1328561(11-20)Online publication date: 11-Nov-2007
https://dl.acm.org/doi/10.1145/1328554.1328561
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FCCM '95: Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines

April 1995

ISBN:081867086X

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IEEE Computer Society

United States

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Published: 19 April 1995

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Neely CBrebner GShang W(2013)ReShapeACM Transactions on Reconfigurable Technology and Systems10.1145/2457443.24574486:1(1-23)Online publication date: 1-May-2013
El-Araby EGonzalez IEl-Ghazawi T(2009)Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable ComputingACM Transactions on Reconfigurable Technology and Systems10.1145/1462586.14625901:4(1-23)Online publication date: 1-Jan-2009
El-Araby EGonzalez IEl-Ghazawi TKindratenko VEl-Ghazawi T(2007)Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computingProceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC0710.1145/1328554.1328561(11-20)Online publication date: 11-Nov-2007
Hauck SDeHon A(2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
Handa MRadhakrishnan RMukherjee MVemuri R(2003)A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA DesignsProceedings of the 16th International Conference on VLSI Design10.5555/832285.835601Online publication date: 4-Jan-2003
Heron JWoods RSezer STurner R(2001)Development of a Run-Time Reconfiguration System with Low Reconfiguration OverheadJournal of VLSI Signal Processing Systems10.5555/598544.281325928:1-2(97-113)Online publication date: 1-May-2001
Karri RKim KPotkonjak M(2000)Computer Aided Design of Fault-Tolerant Application Specific Programmable ProcessorsIEEE Transactions on Computers10.1109/12.89594249:11(1272-1284)Online publication date: 1-Nov-2000
Heron JWoods R(1999)Accelerating Run-Time Reconfiguration on FCCMsProceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines10.5555/795658.795849Online publication date: 21-Apr-1999
Deshpande DSomani ATyagi AKaptanoglu STrimberger S(1999)Configuration caching vs data caching for striped FPGAsProceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays10.1145/296399.296461(206-214)Online publication date: 1-Feb-1999
Chang DMarek-Sadowska M(1999)Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAsIEEE Transactions on Computers10.1109/12.77379448:6(565-578)Online publication date: 1-Jun-1999
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