[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/275107.275120acmconferencesArticle/Chapter ViewAbstractPublication PagesfpgaConference Proceedingsconference-collections
Article
Free access

Managing pipeline-reconfigurable FPGAs

Published: 01 March 1998 Publication History

Abstract

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2.

References

[1]
J. Babb, R. Tessier, and A. Agarwal. Virtual wires: Overcoming pin limitations in FPGA-based logic emulators. In D. A. Buell and K. L. Pocek, editors, Proceedings o! IEEB Workshop on FPGAs for Custom Computing Machines, pages 142-151, Nape, CA, April 1993.
[2]
N. Bhat, K. Ghaudhary, and E.S. Kuh. Performance-oriented fully routable dynamic architecture for a field programmable logic device. M93/42, 1993. U.O. Berkeley.
[3]
A. DeHon. DPGA-coupled microprocessors: Commodity ICs for the early 21st century. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEB Workshop on FPGAs .for Custom Computing Machines, pages 31-39, Nape, CA, April 1994.
[4]
B. Von Herzen. Signal processing at 250mhz using highperformance FPGAs. In A CM/$IGDA International Symposium on Field Programmable Date Arrays, pages 62-68, Monterey, CA, February 1997.
[5]
Texas Instruments. TMS3:~0C6201 digital signal processor, revision 2, 1997.
[6]
H.T. Kung. Why systolic architectures? In IEEE Computer, pages 37-45, Piscataway, NJ, January 1982.
[7]
W. Luk, N. Shirazi, S.R. Guo, and P.Y.K. Cheung. Pipeline morphing and virtual pipelines. In W. Luk and P. Y. K. Cheung, editors, Field-Programmable Logic and Applications, London, England, September 1997. To be published.
[8]
B. Newgard. Signal processing with Xilinx FPQAs, September 1996. http://www .xilinx. com/appnotes/sd.xdsp, pdf.
[9]
J. Hose. Private communications, 1997.
[10]
H. Schmit. incremental reconfiguration for pipelined applications. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs }or Custom Computing Machines, pages 47-55, Nape, CA, April 1997.
[11]
S. Trimberger. Field programmable gate array with built-in bitstream data expansion. U.S. Patent No. 5,426,379, June 1995.
[12]
S. Trimberger, D. Oarberry, A. Johnson, and J. Wong. A time-multiplexed FPGA. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 22-28, Nape, CA, April 1997.

Cited By

View all
  • (2018)Recognized as the Best: The ACM\/SIGDA TCFPGA Hall of Fame for FPGAs and Reconfigurable ComputingIEEE Solid-State Circuits Magazine10.1109/MSSC.2018.282286110:2(30-35)Online publication date: Sep-2019
  • (2017)Pipeline Reconfigurable DSP for Dynamically Reconfigurable ArchitecturesCircuits, Systems, and Signal Processing10.1007/s00034-017-0493-x36:9(3799-3824)Online publication date: 1-Sep-2017
  • (2016)VLSI architecture for color mosaic image/video sequences2016 International Conference on Inventive Computation Technologies (ICICT)10.1109/INVENTIVE.2016.7830242(1-6)Online publication date: Aug-2016
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
March 1998
262 pages
ISBN:0897919785
DOI:10.1145/275107
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 March 1998

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Article

Conference

FPGA98
Sponsor:
FPGA98: 1998 International Symposium on Field Programmable Gate Arrays
February 22 - 25, 1998
California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)84
  • Downloads (Last 6 weeks)13
Reflects downloads up to 18 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2018)Recognized as the Best: The ACM\/SIGDA TCFPGA Hall of Fame for FPGAs and Reconfigurable ComputingIEEE Solid-State Circuits Magazine10.1109/MSSC.2018.282286110:2(30-35)Online publication date: Sep-2019
  • (2017)Pipeline Reconfigurable DSP for Dynamically Reconfigurable ArchitecturesCircuits, Systems, and Signal Processing10.1007/s00034-017-0493-x36:9(3799-3824)Online publication date: 1-Sep-2017
  • (2016)VLSI architecture for color mosaic image/video sequences2016 International Conference on Inventive Computation Technologies (ICICT)10.1109/INVENTIVE.2016.7830242(1-6)Online publication date: Aug-2016
  • (2013)Meta-algorithms for scheduling a chain of coarse-grained tasks on an array of reconfigurable FPGAsVLSI Design10.1155/2013/2495922013(3-3)Online publication date: 1-Jan-2013
  • (2013)Multiple-View Information Reduction Techniques for WMSN Using Image StitchingWireless Multimedia Sensor Networks on Reconfigurable Hardware10.1007/978-3-642-38203-1_7(207-248)Online publication date: 23-Jul-2013
  • (2013)Single-View Information Reduction Techniques for WMSN Using Event CompressionWireless Multimedia Sensor Networks on Reconfigurable Hardware10.1007/978-3-642-38203-1_6(159-206)Online publication date: 23-Jul-2013
  • (2013)Single-View Information Reduction Techniques for WMSN Using Event DetectionWireless Multimedia Sensor Networks on Reconfigurable Hardware10.1007/978-3-642-38203-1_5(105-157)Online publication date: 23-Jul-2013
  • (2013)FPGA Wireless Multimedia Sensor Node Hardware PlatformsWireless Multimedia Sensor Networks on Reconfigurable Hardware10.1007/978-3-642-38203-1_4(69-103)Online publication date: 23-Jul-2013
  • (2013)Hardware Technology and Programming Languages for Reconfigurable DevicesWireless Multimedia Sensor Networks on Reconfigurable Hardware10.1007/978-3-642-38203-1_3(39-68)Online publication date: 23-Jul-2013
  • (2013)Wireless Multimedia Sensor Network TechnologyWireless Multimedia Sensor Networks on Reconfigurable Hardware10.1007/978-3-642-38203-1_2(5-38)Online publication date: 23-Jul-2013
  • Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media