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Asynchronous interface specification, analysis and synthesis

Published: 01 May 1998 Publication History

Abstract

Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed mod ules/agents without common clock. However, the most recent developments in the the ory of asynchronous design in the areas of specifications, mo dels, analysis, verification, synthesis, technology mapping, timing optimization and performanc e analysis are not widely known and r arely accepted by industry.
The go al of this tutorial is to fill this gap and to present an overview of one p opular systematic design methodology for design of asynchronous interface controllers. This metho dology is based on using P etri nets (PN) a formal mo del that, from the engine ering standpoint, is a formalization of timing diagrams (waveforms) and from the system designer standpoint is a concurrent state machine, in which lo cal comp onents can perform indep endent or interdependent concurrent actions, changing their local states asynchronously. We will introduce this mo del informally b ased on a simple example: a VME-bus controller serving reads from a devic e to a bus and writes f rom the bus into the devic e.

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  • (2008)Slack analysis in the system design loopProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450189(231-236)Online publication date: 19-Oct-2008
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cover image ACM Conferences
DAC '98: Proceedings of the 35th annual Design Automation Conference
May 1998
820 pages
ISBN:0897919645
DOI:10.1145/277044
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 May 1998

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DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference
June 15 - 19, 1998
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Cited By

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  • (2012)Interface circuit synthesis of system-on-chipInternational Journal of Electronics10.1080/00207217.2011.65169299:7(957-970)Online publication date: Jul-2012
  • (2008)Slack analysis in the system design loopProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450189(231-236)Online publication date: 19-Oct-2008
  • (2008)MOCSYN: Multiobjective Core-Based Single-Chip System SynthesisDesign, Automation, and Test in Europe10.1007/978-1-4020-6488-3_22(291-311)Online publication date: 2008
  • (2007)A New Time Independent Asynchronous Protocol and Its ApplicationsIEEE Transactions on Industrial Informatics10.1109/TII.2007.8984393:2(143-153)Online publication date: May-2007
  • (2006)A Novel Time Independent Asynchronous Communication Protocol&Its ApplicationsIECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics10.1109/IECON.2006.347420(3574-3579)Online publication date: Nov-2006
  • (2002)Symbolic model checking of Dual Transition Petri NetsProceedings of the tenth international symposium on Hardware/software codesign10.1145/774789.774799(43-48)Online publication date: 6-May-2002
  • (2001)Towards synthesis of monotonic asynchronous circuits from signal transition graphsProceedings Second International Conference on Application of Concurrency to System Design10.1109/CSD.2001.981775(179-188)Online publication date: 2001
  • (1999)CAD directions for high performance asynchronous circuitsProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309893(116-121)Online publication date: 1-Jun-1999
  • (1999)MOCSYNProceedings of the conference on Design, automation and test in Europe10.1145/307418.307502(55-es)Online publication date: 1-Jan-1999
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