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Application-aware adaptive cache architecture for power-sensitive mobile processors

Authors:

Garo Bournoutian,

Alex OrailogluAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 13, Issue 3

Article No.: 41, Pages 1 - 26

https://doi.org/10.1145/2539036.2539037

Published: 24 December 2013 Publication History

Abstract

Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for general-purpose processors. All the while, it is also expected that these mobile processors be power-conscientious as well as of minimal area impact. These devices pose unique usage demands of ultra-portability but also demand an always-on, continuous data access paradigm. As a result, this dichotomy of continuous execution versus long battery life poses a difficult challenge. This article explores a novel approach to mitigating mobile processor power consumption while abating any significant degradation in execution speed. The concept relies on efficiently leveraging both compile-time and runtime application memory behavior to intelligently target adjustments in the cache to significantly reduce overall processor power, taking into account both the dynamic and leakage power footprint of the cache subsystem. The simulation results show a significant reduction in power consumption of approximately 13% to 29%, while only incurring a nominal increase in execution time and area.

References

[1]

Agarwal, A., Li, H., and Roy, K. 2002. DRG-cache: A data retention gated-ground cache for low power. In Proceedings of the 39th Conference on Design Automation (DAC'02). 473--478.

Digital Library

[2]

Agarwal, A. and Pudar, S. D. 1993. Column-associative caches: A technique for reducing the miss rate of direct-mapped caches. SIGARCH Comput. Architect. News, 21, 2, 179--190.

Digital Library

[3]

Albonesi, D. H. 1999. Selective cache ways: On-demand cache resource allocation. In Proceedings of the 32nd International Symposium on Microarchitecture (MICR0'32). 248--259.

Digital Library

[4]

Austin, T., Larson, E., and Ernst, D. 2002. SimpleScalar: An infrastructure for computer system modeling. Computer 35, 2, 59--67.

Digital Library

[5]

Bournoutian, G. and Orailoglu, A. 2008. Miss reduction in embedded processors through dynamic, power-friendly cache design. In Proceedings of the 45th Conference on Design Automation (DAC'08). 304--309.

Digital Library

[6]

Bournoutian, G. and Orailoglu, A. 2010. Dynamic, non-linear cache architecture for power-sensitive mobile processors. In Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS'10). 187--194.

Digital Library

[7]

Brooks, D., Tiwari, V., and Martonosi, M. 2000. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA'00). 83--94.

Digital Library

[8]

Calder, B., Grunwald, D., and Emer, J. 1996. Predictive sequential associative cache. In Proceedings of the 2nd Symposium on High-Performance Computer Architecture (HPCA'96). 244--253.

Digital Library

[9]

Flautner, K., Kim, N. S., Martin, S., Blaauw, D., and Mudge, T. 2002. Drowsy caches: Simple techniques for reducing leakage power. SIGARCH Comput. Architect. News 30, 2, 148--157.

Digital Library

[10]

Ghose, K. and Kamble, M. B. 1999. Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'99). 70--75.

Digital Library

[11]

Gordon-Ross, A., Vahid, F., and Dutt, N. 2009. Fast configurable-cache tuning with a unified second-level cache. IEEE Trans. Very Large Scale Integ. Syst. 17, 1, 80--91.

Digital Library

[12]

Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., and Brown, R. B. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the International Workshop on Workload Characterization (WWC'01). 3--14.

Digital Library

[13]

Hasegawa, A., Kawasaki, I., Yamada, K., Yoshioka, S., Kawasaki, S., and Biswas, P. 1995. SH3: High code density, low power. IEEE Micro 15, 6, 11--19.

Digital Library

[14]

Inoue, K., Ishihara, T., and Murakami, K. 1999. Way-predicting set-associative cache for high performance and low energy consumption. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'99). 273--275.

Digital Library

[15]

ITRS. 2009. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2009. http://www.itrs.net/.

[16]

Jouppi, N. P. 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. SIGARCH Comput. Architect. News, 18, 2SI, 364--373.

Digital Library

[17]

Kin, J., Gupta, M., and Mangione-Smith, W. H. 1997. The filter cache: An energy efficient memory structure, In Proceedings of the 30th Intenational Symposium on Microarchitecture (MICRO'30). 184--193.

Digital Library

[18]

Ko, U., Balsara, P. T., and Nanda, A. K. 1995. Energy optimization of multi-level processor cache architectures. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'95). 45--49.

Digital Library

[19]

Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 1997. MediaBench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the 30th International symposium on Microarchitecture (MICRO30). 330--335.

Digital Library

[20]

Lee, L., Kannan, S., and Fridman, J. 2004. MPEG4 video codec on a wireless handset baseband system. In Proceedings of the Workshop Media and Signal Processors for Embedded Systems and SoCs.

[21]

Malik, A., Moyer, B., and Cermak, D. 2000. A low power unified cache architecture providing power and performance flexibility. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00). 241--243.

Digital Library

[22]

Mamidipaka, M. and Dutt, N. 2004. eCACTI: An enhanced power estimation model for on-chip caches. University of California, Irvine Center for Embedded Computer Systems. Tech. rep. TR-04-28.

[23]

Nethercote, N. and Seward, J. 2007. Valgrind: A framework for heavyweight dynamic binary instrumentation. In Proceedings of the Conference on Programming Language Design and Implementation (PLDI'07). 89--100.

Digital Library

[24]

Powell, M., Yang, S.-H., Falsafi, B., Roy, K., and Vijaykumar, T. N. 2000. Gated-V_dd: A circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00). 90--95.

Digital Library

[25]

Rodriguez, S. and Jacob, B. 2006. Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'06). 25--30.

Digital Library

[26]

SPEC. 2000. SPEC CPU2000 Benchmarks. http://www.spec.org/cpu/.

[27]

Sundararajan, K. T., Jones, T. M., and Topham, N. 2011. Smart cache: A self adaptive cache architecture for energy efficiency. In Proceedings of the International Conference on Embedded Computer Systems (SAMOS'11). 41--50.

[28]

Wilton, S. J. E. and Jouppi, N. P. 1996. CACTI: An enhanced cache access and cycle time model. IEEE J. Solid-State Circuits 31, 5, 677--688.

Cited By

Navarro OYudi JHoffmann JHernandez HHübner M(2020)A Machine Learning Methodology for Cache Memory Design Based on Dynamic InstructionsACM Transactions on Embedded Computing Systems10.1145/337692019:2(1-20)Online publication date: 11-Mar-2020
https://dl.acm.org/doi/10.1145/3376920
Mallya NPatil GRaveendran B(2015)Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors2015 28th International Conference on VLSI Design10.1109/VLSID.2015.16(65-70)Online publication date: Jan-2015
https://doi.org/10.1109/VLSID.2015.16

Index Terms

Application-aware adaptive cache architecture for power-sensitive mobile processors
1. Computer systems organization
2. Hardware
  1. Robustness

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Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 13, Issue 3

December 2013

385 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2539036

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 24 December 2013

Accepted: 01 December 2012

Revised: 01 October 2011

Received: 01 March 2011

Published in TECS Volume 13, Issue 3

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Cited By

Navarro OYudi JHoffmann JHernandez HHübner M(2020)A Machine Learning Methodology for Cache Memory Design Based on Dynamic InstructionsACM Transactions on Embedded Computing Systems10.1145/337692019:2(1-20)Online publication date: 11-Mar-2020
https://dl.acm.org/doi/10.1145/3376920
Mallya NPatil GRaveendran B(2015)Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors2015 28th International Conference on VLSI Design10.1109/VLSID.2015.16(65-70)Online publication date: Jan-2015
https://doi.org/10.1109/VLSID.2015.16

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